Advantech AIMB-210 user manual Lvds Invert INV1 & INV2 Optional, System I/O Ports

B.22 LVDS Invert: INV1 & INV2 (Optional)

Table B.23: LVDS Power Jumper

Pin Signal

1VCC12

2GND

3BKLTEN

4VBR

5 VCC

B.23 System I/O Ports

Table B.24: System I/O Ports

Addr. range (Hex)	Device
000-01F	Interrupt controller 1, master
022-023	Chipset address
040-05F	8254 timer
060-06F	8042 (keyboard controller)
070-07F	Real-time clock, non-maskable interrupt (NMI) mask
080-09F	DMA page register
0A0-0BF	Interrupt controller 2
0C0-0DF	DMA controller
0F0	Clear math co-processor
0F1	Reset math co-processor
0F8-0FF	Math co-processor
1F0-1F8	Fixed disk
200-207	Game I/O
278-27F	Parallel printer port 2 (LPT3)
290-297	On-board hardware monitor
2F8-2FF	Serial port 2
360-36F	Reserved
378-37F	Parallel printer port 1 (LPT2)
380-38F	SDLC, bisynchronous 2
3A0-3AF	Bisynchronous 1
3B0-3BF	Monochrome display and printer adapter (LPT1)
3C0-3CF	Reserved
3D0-3DF	Color/graphics monitor adapter
3F0-3F7	Diskette controller
3F8-3FF	Serial port 1
4E0-4E7	Serial port 4
3E8-3EF	Serial port 6
4F0-4F8	Serial port 3
4F8-4FF	Serial port 5

Appendix B I/O Pin Assignments

81 AIMB-210 User Manual