Table C.1: Register Offset Address Table
22h | W | Counter Command Enable Register | CE CE | |
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| R | Interrupt Status Register | 1 | 0 |
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| DI DIB DIA C1 | C0 | |
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| C |
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24h | W | Interrupt Clear |
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| R | N/A |
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2Ch | W | I/O Direction Control Register |
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| PA PC | PB | PC |
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| H |
| L |
RN/A 2Eh W N/A
R Port A Interrupt Status Register
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| Bit7 | Bit | Bit | Bit | Bit | Bit2 | Bit1 | Bit0 | Bit7 |
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| 6 | 5 | 4 | 3 |
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30h | W | N/A |
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| R | Port | B Interrupt Status Register |
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| Bit7 | Bit | Bit | Bit | Bit | Bit2 | Bit1 | Bit0 | Bit7 |
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| 6 | 5 | 4 | 3 |
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32h | W | N/A |
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| R | Port | C Interrupt Status Register |
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| Bit7 | Bit | Bit | Bit | Bit | Bit2 | Bit1 | Bit0 | Bit7 |
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| 6 | 5 | 4 | 3 |
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38h | W | FOUT0 Register |
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| FOE |
| FS2 | FS1 | FS0 |
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| DV | DV | DV | DV |
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| 3 | 2 | 1 | 0 |
| R | N/A |
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3Ah | W | FOUT1 Register |
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| FOE |
| FS2 | FS1 | FS0 |
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| DV | DV | DV | DV |
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| 3 | 2 | 1 | 0 |
| R | Port | C Interrupt Status Register |
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34 |
