C.10 |
| Interrupt Clear Register |
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Write any data to these two bytes to clear the interrupt. |
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Address |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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24h | W | Interrupt Clear |
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C.11 | I/O Direction Control Register |
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Address + | 15 14 13 12 11 10 9 8 7 6 5 4 | 3 | 2 | 1 | 0 | |
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2Ch | W | I/O Direction Control Register |
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| PA | PCH |
| PB | PCL |
| R | I/O Direction Control Register |
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| PA | PCH |
| PB | PCL |
1.I/O Direction Control Bit:
0= Output
1= Input
C.12 Port A/B/C Interrupt Status Register
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Address | 15 | 14 | 13 | 12 | 11 | 10 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
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2Eh | W | Port A Interrupt Status Register |
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| N/A |
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| R | Port A Interrupt Status Register | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | |||||||
30h | W | Port B Interrupt Status Register | |||||||||||||||
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| N/A |
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| R | Port B Interrupt Status Register | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | |||||||
32h | W | Port C Interrupt Status Register | |||||||||||||||
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| N/A |
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| R | Port C Interrupt Status Register | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | |||||||
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1.Bit7 to Bit0: Port A/B/C Interrupt Status Register
0= No interrupt occurred
1= Interrupt occurred
40 |