Agilent Technologies E1470A user manual Register Definitions, Table B-2. Register Map

Table B-1. General Register-based Programming Method

System	Typical Commands	Base Address
External Computer	VXI:READ? logical_address, offset	Module Logical Address setting (LADDR*)
(over GPIB to E1406	VXI:WRITE logical_address,offset,data	offset = register number
Command Module)
	DIAG:PEEK? (Base_addr + offset,width)	Base_addr = 1FC000h + (LADDR * 40)h or
	DIAG:POKE (Base_addr +offset,width, data)	= 2,080,768 + (LADDR * 64)
	When using DIAG:PEEK? and DIAG:POKE, the	offset = register number
	width must be either 8 or 16.
* LADDR = E1470 Logical Address = 120 / 8 = 15

Reset and Registers When the E1470A undergoes power-on or a *RST in SCPI, the bits of the registers are put into the following states. Manufacturer ID Register, Device Type Register, and Status/Control Register are unaffected and Relay Control Registers have a “0” written to each bit. This forces all relays to their power-on/reset state. To reset the module, write a “1” and then a “0” to bit 0 of the Status/Control Register.

Register Definitions

You can program the E1470A Cascade RF Switch module using its hardware registers. The procedures for reading or writing to a register depend on your operating system and programming language. Whatever the access method, you will need to identify each register with its address. These addresses are given in Table B-2.

Table B-2. Register Map

Register Name	Address
Manufacturer ID (read only register)	Base + 00h
Device ID (read only register)	Base + 02h
Card /Status/Control (read/write register)	Base + 04h
Relay Control Register (read/write register)	Base + 20h
Relay Control Register (read/write register)	Base + 22h
Relay Control Register (read/write register)	Base + 24h
Relay Control Register (read/write register)	Base + 26h
Relay Control Register (read/write register)	Base + 28h

The interrupt protocol supported is “release on interrupt acknowledge.”

An interrupt is cleared by a VXIbus interrupt acknowledge cycle.

44 Register-Based Programming Appendix B