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HSC-ADC-EVALC
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Fpga to Sram Data
Models:
HSC-ADC-EVALC
1
11
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Functional Block Diagram
Configuration Eeprom
Connection and Setup
Connector J2
U4 DIP Switch Setting
Sram and Fpga Power
Page 11
Image 11
HSC-ADC-EVALC
FPGA TO SRAM DATA
XC4VFX20-10FFG672C
XC4VFX20-10FFG672C
06676-007
Figure 7.
Rev. 0 Page 11 of 32
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Image 11
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Contents
Product Highlights
Features
Functional Block Diagram
Equipment Needed
HSC-ADC-EVALC Table of Contents
Evaluation Board Description
HSC-ADC-EVALC
Product Description
HSC-ADC-EVALC ADC Capture Board Easy Start
Power Supplies
Connection and Setup
Jumper Number Description
U4 DIP Switch Setting
Jumpers
HSC-ADC-EVALC Components Top View
HSC-ADC-EVALC ADC Capture Board Features
HSC-ADC-EVALC Components Bottom View
HSC-ADC-EVALC Supported ADC Evaluation Boards
HSC-ADC-EVALC Theory of Operation
HSC-ADC-EVALC Schematics
HSC-ADC-EVALC Evaluation Board Schematics and Artwork
Sram Address and Control
Fpga to Sram Data
AD19 to be Used with Higher Density Sram Devices
Sram and Fpga Power
Sram a Bypass CAP
Unused Rocket I/0 Connections
Rocket I/0 Connections
USB Connections
Rev Page 18
EZ-KIT Expansion Interface for DSPs
Tyco HM
Configuration Eeprom
Power and Voltage Regulators
Top Silkscreen
PCB Layout
HSC-ADC-EVALC
J1 HS-SERIAL/SPI/AUX
Schematic Net Name Fpga Pin
Connector J2
HSC-ADC-EVALC J3 I/O Connections to Fpga U1
Connector J3
Part Number
HSC-ADC-EVALC Ordering Information
Qty
Manufacturer
R16
Qty Reference Designator Description
Model Description
Ordering Guide ESD Caution
Rev Page 31
Rev Page 32
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Contents