HSC-ADC-EVALC Components Top View | Analog Devices instruction

HSC-ADC-EVALC

HSC-ADC-EVALC ADC CAPTURE BOARD FEATURES

GENERAL PURPOSE I/O,
USB/SPI CONTROL	DATA BUS 1	DATA BUS 2

XILINX

VIRTEX-4

FPGA

DEBUG

PINS

EXTERNAL

SYNC I/O

CYPRESS USB	USB CONNECTOR	FPGA JTAG	5VDC POWER
CONTROLLER		CONNECTOR	INPUT

Figure 3. HSC-ADC-EVALC Components (Top View)

FPGA LOAD

SELECT

ON BOARD POWER SUPPLY

100MHz

OSCILLATOR

FPGA I/O VOLTAGE MODE

FPGA CONFIG PROM

06676-002

Rev. 0 Page 6 of 32

Image 6

Analog Devices warranty HSC-ADC-EVALC ADC Capture Board Features, HSC-ADC-EVALC Components Top View

Contents

Equipment Needed FeaturesFunctional Block Diagram Product Highlights HSC-ADC-EVALC Table of Contents HSC-ADC-EVALC Product DescriptionEvaluation Board Description Power Supplies Connection and SetupHSC-ADC-EVALC ADC Capture Board Easy Start U4 DIP Switch Setting JumpersJumper Number Description HSC-ADC-EVALC ADC Capture Board Features HSC-ADC-EVALC Components Top View HSC-ADC-EVALC Supported ADC Evaluation Boards HSC-ADC-EVALC Components Bottom View HSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Evaluation Board Schematics and Artwork HSC-ADC-EVALC Schematics Sram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators PCB Layout Top Silkscreen HSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Connector J2 Schematic Net Name Fpga Pin Connector J3 HSC-ADC-EVALC J3 I/O Connections to Fpga U1 Manufacturer HSC-ADC-EVALC Ordering InformationQty Part Number Qty Reference Designator Description R16 Ordering Guide ESD Caution Model Description Rev Page 31 Rev Page 32