Manuals
/
Brands
/
TV and Video
/
TV Converter Box
/
Analog Devices
/
TV and Video
/
TV Converter Box
Analog Devices
HSC-ADC-EVALC
- page 16
1
16
32
32
Download
32 pages, 2.05 Mb
HSC-ADC-EVALC
Rev. 0 | Page 16 of 32
06676-012
ROCKET I/0 CONNECTIONS
Figure 12.
Contents
Main
High Speed Converter Evaluation Platform
FEATURES
EQUIPMENT NEEDED
PRODUCT HIGHLIGHTS
4. Up to 644 MSPS SDR/800 MSPS DDR Encode Rates on
FUNCTIONAL BLOCK DIAGRAM
HSC-ADC-EVALC
TABLE OF CONTENTS
PRODUCT DESCRIPTION
EVALUATION BOARD DESCRIPTION
HSC-ADC-EVALC
EVALUATION BOARD HARDWARE
HSC-ADC-EVALC ADC CAPTURE BOARD EASY START
Requirements
Easy Start Steps
JUMPERS
Default Settings
Table 2. FPGA Configuration Mode
HSC-ADC-EVALC ADC CAPTURE BOARD FEATURES
Figure 3. HSC-ADC-EVALC Components (Top View)
HSC-ADC-EVALC SUPPORTED ADC EVALUATION BOARDS
HSC-ADC-EVALC
THEORY OF OPERATION
CONFIGURATION
INPUT CIRCUITRY
DATA CAPTURE
HSC-ADC-EVALC
EVALUATION BOARD SCHEMATICS AND ARTWORK
HSC-ADC-EVALC SCHEMATICS
TYCO AND DSP EZKIT CONNE CTOR TO FPGA
SRAM ADDRESS AND CONTROL
FPGA CONTROLS
Figure 6.
Page
Page
SRAM AND FPGA POWE
R
Page
Page
Page
USB CONNECTIONS
USB CONNECTIONS (CONTINUED)
J6
Figure 14.
Page
TYCO HM Zd CONNECTORS
Page
POWER AND VOLTAGE REGULATORS
Figure 18.
PCB LAYOUT
Figure 19. Top Silkscreen
Figure 20. Bottom Silkscreen
I/O CONNECTORJ1, J2, AND J3 PIN MAPPING
(J2) DATA BUS 1(J3) DATA BUS 2
Figure 21. J2 and J3 Pin Mapping
(J1) HS-SERIAL/SPI/AUX
HS-SERIAL/SPI/AUX
Figure 22. J1 Pin Mapping
J1 J2 DATA BUS 1
Table 3. HSC-ADC-EVALC J1 I/O Connections to FPGA (U1)
Table 4. HSC-ADC-EVALC J2 I/O Connections to FPGA (U1)
Table 5. HSC-ADC-EVALC J3 I/O Connections to FPGA (U1)
HSC-ADC-EVALC
ORDERING INFORMATION
BILL OF MATERIALS (RoHS COMPLIANT)
Table 6.
Page
ORDERING GUIDE
ESD CAUTION