Rev Page 31 | Analog Devices HSC-ADC-EVALC instruction

HSC-ADC-EVALC

NOTES

Rev. 0 Page 31 of 32

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Analog Devices HSC-ADC-EVALC warranty Rev Page 31

Contents

Product Highlights FeaturesFunctional Block Diagram Equipment Needed HSC-ADC-EVALC Table of Contents Product Description HSC-ADC-EVALCEvaluation Board Description Connection and Setup Power SuppliesHSC-ADC-EVALC ADC Capture Board Easy Start Jumpers U4 DIP Switch SettingJumper Number Description HSC-ADC-EVALC Components Top View HSC-ADC-EVALC ADC Capture Board Features HSC-ADC-EVALC Components Bottom View HSC-ADC-EVALC Supported ADC Evaluation Boards HSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Schematics HSC-ADC-EVALC Evaluation Board Schematics and Artwork Sram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators Top Silkscreen PCB Layout HSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Schematic Net Name Fpga Pin Connector J2 HSC-ADC-EVALC J3 I/O Connections to Fpga U1 Connector J3 Part Number HSC-ADC-EVALC Ordering InformationQty Manufacturer R16 Qty Reference Designator Description Model Description Ordering Guide ESD Caution Rev Page 31 Rev Page 32