Configuration Eeprom | Analog Devices HSC-ADC-EVALC instruction

R77

100Ω

R78

100Ω

R75

3.74KΩ

R76

3.74KΩ

HSC-ADC-EVALC

CONFIGURATION EEPROM

R73

ZERO

JTAG CONNECTOR	EEPROM HARDWARE
	RECONFIGURATION
	PUSHBUTTON

R57

3.74KΩ

06676-017

Figure 17.

Rev. 0 Page 21 of 32

Image 21

Analog Devices HSC-ADC-EVALC warranty Configuration Eeprom

Contents

Functional Block Diagram FeaturesEquipment Needed Product Highlights HSC-ADC-EVALC Table of Contents HSC-ADC-EVALC Product DescriptionEvaluation Board Description Power Supplies Connection and SetupHSC-ADC-EVALC ADC Capture Board Easy Start U4 DIP Switch Setting JumpersJumper Number Description HSC-ADC-EVALC Components Top View HSC-ADC-EVALC ADC Capture Board Features HSC-ADC-EVALC Components Bottom View HSC-ADC-EVALC Supported ADC Evaluation Boards HSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Schematics HSC-ADC-EVALC Evaluation Board Schematics and Artwork Sram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators Top Silkscreen PCB Layout HSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Schematic Net Name Fpga Pin Connector J2 HSC-ADC-EVALC J3 I/O Connections to Fpga U1 Connector J3 Qty HSC-ADC-EVALC Ordering InformationManufacturer Part Number R16 Qty Reference Designator Description Model Description Ordering Guide ESD Caution Rev Page 31 Rev Page 32