HSC-ADC-EVALC
HIGH SPEED SERIAL
REFERENCE CLK
HIGH SPEED SERIAL
DATA INPUTS
FUTURE HIGH SPEED SERIAL DATA INPUTS
FPGA GENERAL
PURPOSE I/O
SPI CONTROL (3.3V)
USB DIRECT I/O (3.3V)
D |
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C |
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| C |
B |
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| B |
A |
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| A |
MGTCLK1– | SD1– | SD2– | SD3– | SD4– | SD5– | SD6– | SD7– | SD8– | MGTCLK2– |
MGTCLK1+ | SD1+ | SD2+ | SD3+ | SD4+ | SD5+ | SD6+ | SD7+ | SD8+ | MGTCLK2+ |
I/O_1 | I/O_3 | I/O_5 | I/O_7 | SCLK | SDI | SDO | USB_1 | USB_2 | USB_4 |
I/O_2 | I/O_4 | I/O_6 | I/O_8 CSB_1 CSB_2 | CSB_3 | CSB_4 | USB_3 | USB_5 | ||
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Figure 22. J1 Pin Mapping
13.843mm | 38mm | 32mm | 43.155mm |
1.4mm |
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J1
J2
| J3 |
DATA BUS 1 | DATA BUS 2 |
Figure 23. Data Converter I/O Connector Placement (Top View)
Rev. 0 Page 25 of 32
