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Software Configuration Guide—Release 12.2(25)SG
OL-7659-03
Chapter39 Diagnostics on the Catalyst 4500 Switch
Sample POST Results
For all the supervisor engines, POST performs CPU, traffic, system, system memory, and feature tests.
For CPU tests, POST verifies appropriate activity of the supervisor SEEPROM, temperature sensor, and
Ethernet-end-of-band channel (eobc), when used.
The following example illustrates the output of a CPU subsystem test on all supervisor engines except
the WS-X4013+TS:
[..]
Cpu Subsystem Tests ...
seeprom: . temperature_sensor: . eobc: .
[..]
The following example illustrates the output of a CPU subsystem test on a WS-X4013+TS supervisor
engine.
[..]
Cpu Subsystem Tests ...
seeprom: . temperature_sensor: .
[..]
For traffic tests, POST sends packets from the CPU to the switch. These packets loop several times
within the switch core and validate the switching, the Layer 2 and the Layer 3 functionality. To isolate
the hardware failures accurately, the loop back is done both inside and outside the switch ports.
The following example illustrates the output of a Layer 2 traffic test at the switch ports on the supervisor
engines WS-X4516, WS-X4516-10GE, WS-X4013+10GE, WS-C4948G-10GE:
Port Traffic: L2 Serdes Loopback ...
0: . 1: . 2: . 3: . 4: . 5: . 6: . 7: . 8: . 9: . 10: . 11: .
12: . 13: . 14: . 15: . 16: . 17: . 18: . 19: . 20: . 21: . 22: . 23: .
24: . 25: . 26: . 27: . 28: . 29: . 30: . 31: . 32: . 33: . 34: . 35: .
36: . 37: . 38: . 39: . 40: . 41: . 42: . 43: . 44: . 45: . 46: . 47: .
The following example illustrates the output of a Layer 2 traffic test at the switch ports on the supervisor
engines WS-X4013+TS, WS-X4515, WS-X4013+, WS-X4014, WS-C4948G :
Port Traffic: L2 Serdes Loopback ...
0: . 1: . 2: . 3: . 4: . 5: . 6: . 7: . 8: . 9: . 10: . 11: .
12: . 13: . 14: . 15: . 16: . 17: . 18: . 19: . 20: . 21: . 22: . 23: .
24: . 25: . 26: . 27: . 28: . 29: . 30: . 31:
POST also performs tests on the packet and system memory of the switch. These are n umbered
dynamically in ascending order starting with 1 and repres ent different memories.
The following example illustrates the output from a system memory test:
Switch Subsystem Memory ...
1: . 2: . 3: . 4: . 5: . 6: . 7: . 8: . 9: . 10: . 11: . 12: .
13: . 14: . 15: . 16: . 17: . 18: . 19: . 20: . 21: . 22: . 23: . 24: .
25: . 26: . 27: . 28: . 29: . 30: . 31: . 32: . 33: . 34: . 35: . 36: .
37: . 38: . 39: . 40: . 41: . 42: . 43: . 44: . 45: . 46: . 47: . 48: .
49: . 50: . 51: . 52: . 53: . 54: . 55: .
POST also tests the Netflow services card (Supervisor Engine IV and Supervi sor Engine V) and the
Netflow services feature (Supervisor Engine V -10GE). Failures from these tests are treated as marginal,
as they do not impact functionality of the switch (except for the unavailability of the Netflow features):
Netflow Services Feature ...
se: . cf: . 52: . 53: . 54: . 55: . 56: . 57: . 58: . 59: . 60: . 61: .
62: . 63: . 64: . 65: .