PRELIMINARY CY14B104K, CY14B104M

4 Mbit (512K x 8/256K x 16) nvSRAM withReal Time Clock
CypressSemiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-07103 Rev. *K Revised January 29, 2009

Features

■20 ns, 25 ns, and 45 ns access times
■Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
■Hands off automatic STORE on power down with only a small
capacitor
■STORE to QuantumTrap® nonvolatile elements is initiated by
software, device pin, or AutoStore® on power down
■RECALL to SRAM initiated by software or power up
■High reliability
■Infinite Read, Write, and RECALL cycles
■200,000 STORE cycles to QuantumTrap
■20 year data retention
■Single 3V +20%, –10% operation
■Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
■Watchdog timer
■Clock alarm with programmable interrupts
■Capacitor or battery backup for RTC
■Commercial and industrial temperatures
■44 and 54-pin TSOP II package
■Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104K/CY14B104M combines a 4-Mbit
nonvolatile static RAM with a full featured Real Time Clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days or months alarms. There is also a programmable watchdog
timer for process control.
STATICRAM
ARRAY
2048X2048
R
O
W
D
E
C
O
D
E
R
COLUMNI/O
COLUMNDEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum
Trap
2048X2048
STORE
RECALL
VCC
VCA
P
HSB
A9A10A11 A12 A13 A14 A15 A16
SOFTWARE
DETECT A14-A
2
OE
CE
WE
BHE
BLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
A18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
RTC
MUX A18-A
0
X1
X2
INT
VRTCbat
VRTCcap
Logic Block Diagram[1, 2, 3]
Notes
1. Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
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