Cypress CY14B104K, CY14B104M AutoStore/Power Up RECALL

PRELIMINARY CY14B104K, CY14B104M

Document #: 001-07103 Rev. *K Page 20 of 31

AutoStore/Power Up RECALL

Parameters Description 20 ns 25 ns 45 ns Unit

Min Max Min Max Min Max

tHRECALL [23] Power Up RECALL Duration 20 20 20 ms

tSTORE [24] STORE Cycle Duration 8 8 8 ms

tDELAY [25] Time Allowed to Complete SRAM Cycle 20 25 25 ns

VSWITCH Low Voltage Trigger Level 2.65 2.65 2.65 V

tVCCRISE VCC Rise Time 150 15 0 150 μs

VHDIS[14] HSB Output Driver Disable Voltage 1.9 1.9 1.9 V

tLZHSB HSB To Output Active Time 5 5 5 μs

tHHHD HSB High Active Time 500 500 500 ns

Switching Waveforms

Figure 12. AutoStore or Power Up RECALL[26]

VSWITCH

VHDIS

VVCCRISE tSTORE tSTORE

tHHHD tHHHD

tDELAY

tDELAY

tLZHSB tLZHSB

tHRECALL

tHRECALL

HSBOUT

Autostore

POWER-

UP

RECALL

Read& Write

Inhibited

(RWI)

POWER-UP

RECALL

Read& W rite BROWN

OUT

Autostore

POWER-UP

RECALL

Read& Wri te POWER

DOWN

Autostore

Note24 Note24

Note27

Notes

23.tHRECALL starts from the time VCC rises above VSWITCH.

24.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

25.On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY

.

26.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

27.HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.

[+] Feedback

Contents

Main PRELIMINARY CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Features Real Time Clock 20 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14B104K) or 256K x 16 (CY14B104M) Pinouts Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II 44 - TSOP II Top View (not to scale) 54 - TSOP II Top View (not to scale) Device Operation SRAM Read SRAM Write AutoStore Operation PRELIMINARY CY14B104K, CY14B104M Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Software STORE Software RECALL Preventing AutoStore Data Protection Noise Considerations Real Time Clock Operation nvTIME Operation Clock Operations Calibrating the Clock Alarm Watchdog Timer Power Monitor Interrupts Interrupt Register Flags Register Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram X1 X2 V Enable Page Page Page Page PRELIMINARY CY14B104K, CY14B104M Maximum Ratings Operating Range DC Electrical Characteristics AC Test Conditions Data Retention and Endurance Capacitance Thermal Resistance Page AC Switching Characteristics Figure 8. SRAM Read Cycle 2: CE Controlled[3, 16, 20] Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21] Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21] Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22] (Not applicable for RTC register writes) AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Figure 12. AutoStore or Power Up RECALL Software Controlled STORE and RECALL Cycle Figure 13. CE and OE Controlled Software STORE and RECALL Cycle[29] Figure 14. Autostore Enable and Disable Cycle Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Figure 15. Hardware STORE Cycle Figure 16. Soft Sequence Processing Write latch set Truth Table For SRAM Operations For x8 Configuration For x16 Configuration Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C T Ordering Information Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) TOPVIEW BOTTOMVIEW 51-85087 *A Page Document History Page Page Page PRELIMINARY CY14B104K, CY14B104M Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions