Main
PRELIMINARY CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Features
Real Time Clock
20 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
Pinouts
Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II
44 - TSOP II Top View (not to scale)
54 - TSOP II Top View (not to scale)
Device Operation
SRAM Read
SRAM Write
AutoStore Operation
PRELIMINARY CY14B104K, CY14B104M
Hardware STORE (HSB) Operation
Hardware RECALL (Power Up)
Software STORE
Software RECALL
Preventing AutoStore
Data Protection
Noise Considerations
Real Time Clock Operation
nvTIME Operation
Clock Operations
Calibrating the Clock
Alarm
Watchdog Timer
Power Monitor
Interrupts
Interrupt Register
Flags Register
Figure 4. RTC Recommended Component Configuration
Figure 5. Interrupt Block Diagram
X1 X2
V
Enable
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PRELIMINARY CY14B104K, CY14B104M
Maximum Ratings
Operating Range
DC Electrical Characteristics
AC Test Conditions
Data Retention and Endurance
Capacitance
Thermal Resistance
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AC Switching Characteristics
Figure 8. SRAM Read Cycle 2: CE Controlled[3, 16, 20]
Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21]
Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21]
Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22]
(Not applicable for RTC register writes)
AutoStore/Power Up RECALL
Parameters Description 20 ns 25 ns 45 ns Unit
Figure 12. AutoStore or Power Up RECALL
Software Controlled STORE and RECALL Cycle
Figure 13. CE and OE Controlled Software STORE and RECALL Cycle[29]
Figure 14. Autostore Enable and Disable Cycle
Hardware STORE Cycle
Parameters Description 20 ns 25 ns 45 ns Unit
Figure 15. Hardware STORE Cycle
Figure 16. Soft Sequence Processing
Write latch set
Truth Table For SRAM Operations
For x8 Configuration
For x16 Configuration
Part Numbering Nomenclature
CY14 B 104 K ZS P 20 X C T
Ordering Information
Package Diagrams
Figure 17. 44-Pin TSOP II (51-85087)
TOPVIEW BOTTOMVIEW
51-85087 *A
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PRELIMINARY CY14B104K, CY14B104M
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