Data Output High Impedance Output Data Valid

PRELIMINARY	CY14B104K, CY14B104M

Switching Waveforms

Figure 8. SRAM Read Cycle 2: CE Controlled[3, 16, 20]

Address

Address Valid

		tRC	tHZCE
CE		tACE
CE
		tAA
		tLZCE	t
			HZOE
OE		tDOE
OE
		tLZOE	tHZBE
		tDBE
BHE, BLE
		tLZBE
Data Output	High Impedance		Output Data Valid
Data Output		tPU	Output Data Valid
		tPU	tPD
			tPD
ICC	Standby	Active
	Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21]
		tWC
Address		Address Valid
		tSCE	tHA
CE
		tBW
BHE, BLE
		tAW
		tPWE
WE		tSA
		tSA
		tSD	tHD
Data Input			Input Data Valid
		tHZWE	tLZWE
Data Output	Previous Data	High Impedance
Data Output	Previous Data

Notes

21. CE or WE must be >VIH during address transitions.

Document #: 001-07103 Rev. *K

Page 18 of 31

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Cypress CY14B104M Data Output High Impedance Output Data Valid, Standby Active, Address Valid, Data Input Input Data Valid

Contents

Features Functional DescriptionCypress Semiconductor Corporation 198 Champion Court Pinouts Sram Write Device OperationSram Read AutoStore Operation Software Recall Hardware Recall Power UpHardware Store HSB Operation Software Store Preventing AutoStore Mode SelectionA15 A06 Mode Power Store Data Protection Noise ConsiderationsReal Time Clock Operation Alarm Watchdog TimerCalibrating the Clock Interrupts Power MonitorInterrupt Register Flags Register PFE Power Fail Enable WDF Watchdog Timer FlagPF Power Fail Flag AF Alarm Flag Oscen WDSWDF Oscf 0x7FFF9 0x3FFF9 Time Keeping Seconds For the register is Watchdog 0x7FFF5 0x3FFF5 Alarm DayTime-base Write only. Reading it always returns a This condition and write 0 to clear this flag 0x7FFF2 0x3FFF2 Alarm SecondsCenturies 0x7FFF0 0x3FFF0 Flags Document # 001-07103 Rev. *K Maximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating Range Thermal Resistance Data Retention and EnduranceCapacitance AC Test Conditions RTC Battery Pin Voltage RTC Backup CurrentHot Temperature 85 oC RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start Parameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write Cycle Address Valid Data Output High Impedance Output Data ValidStandby Active Data Input Input Data Valid Not applicable for RTC register writes Data Input Data OutputInput Data Valid High Impedance Address Address Valid AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled Store and Recall Cycle Description 20 ns 25 ns 45 ns Unit Min To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse Width Inputs and Outputs Mode Power For x8 ConfigurationFor x16 Configuration Truth Table For Sram Operations Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C T ZS TsopNvsram Ordering Information Package Diagrams Pin Tsop II 51-85160 PCI Document HistoryTUP UHA GVCH/PYRS 6 updated Data protection description Added 20 ns access speed in FeaturesFootnote 1 and 8 referenced for Mode selection Table 6 Updated Starting and stopping the oscillator description Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB

Switching Waveforms

Figure 8. SRAM Read Cycle 2: CE Controlled[3, 16, 20]

BHE, BLE

Data Output

High Impedance

Output Data Valid

Standby

Active

Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21]

Address Valid

Data Input

Input Data Valid

Data Output

Previous Data

High Impedance