Hardware Store Cycle | Cypress CY14B104M, CY14B104K specification

PRELIMINARY

CY14B104K, CY14B104M

Hardware STORE Cycle

Parameters

Description

20 ns

25 ns

45 ns

Unit

Min

Max

Min

Max

Min

Max

tDHSB

HSB

To Output Active Time when write latch not set

20

25

25

ns

tPHSB

Hardware STORE Pulse Width

15

15

15

ns

Switching Waveforms

Figure 15. Hardware STORE Cycle[24]

Write latch set

HSB (IN)

HSB (OUT)

DQ (Data Out)

RWI

tPHSB

tDELAY

tSTORE

tHHHD

tLZHSB

Write latch not set

tPHSB

HSB (IN)

HSB (OUT)

tDELAY

RWI

HSB pin is driven high to VCC only by Internal 100kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

tDHSB

tDHSB

Figure 16. Soft Sequence Processing[32, 33]

	Soft Sequence		tSS	Soft Sequence		tSS
	Command			Command
Address	Address #1	Address #6		Address #1	Address #6
	tSA		tCW		tCW
CE
VCC

Notes

32.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

33.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-07103 Rev. *K

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Cypress CY14B104M, CY14B104K manual Hardware Store Cycle, Description 20 ns 25 ns 45 ns Unit Min, Hardware Store Pulse Width

Contents

Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Pinouts Sram Write Device OperationSram Read AutoStore Operation Software Recall Hardware Recall Power UpHardware Store HSB Operation Software Store Preventing AutoStore Mode SelectionA15 A06 Mode Power Store Noise Considerations Data ProtectionReal Time Clock Operation Watchdog Timer AlarmCalibrating the Clock Interrupts Power MonitorInterrupt Register Flags Register PFE Power Fail Enable WDF Watchdog Timer FlagPF Power Fail Flag AF Alarm Flag WDS OscenWDF Oscf 0x7FFF9 0x3FFF9 Time Keeping Seconds For the register is Watchdog 0x7FFF5 0x3FFF5 Alarm DayTime-base Write only. Reading it always returns a This condition and write 0 to clear this flag 0x7FFF2 0x3FFF2 Alarm SecondsCenturies 0x7FFF0 0x3FFF0 Flags Document # 001-07103 Rev. *K Maximum Ratings DC Electrical CharacteristicsRange Ambient Temperature Operating Range Thermal Resistance Data Retention and EnduranceCapacitance AC Test Conditions RTC Battery Pin Voltage RTC Backup CurrentHot Temperature 85 oC RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start Parameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write Cycle Address Valid Data Output High Impedance Output Data ValidStandby Active Data Input Input Data Valid Not applicable for RTC register writes Data Input Data OutputInput Data Valid High Impedance Address Address Valid AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled Store and Recall Cycle Description 20 ns 25 ns 45 ns Unit Min To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse Width Inputs and Outputs Mode Power For x8 ConfigurationFor x16 Configuration Truth Table For Sram Operations ZS Tsop Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TNvsram Ordering Information Package Diagrams Pin Tsop II 51-85160 PCI Document HistoryTUP UHA GVCH/PYRS 6 updated Data protection description Added 20 ns access speed in FeaturesFootnote 1 and 8 referenced for Mode selection Table 6 Updated Starting and stopping the oscillator description Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB