AC Switching Characteristics, Sram Write Cycle | Cypress CY14B104K

				PRELIMINARY		CY14B104K, CY14B104M
						CY14B104K, CY14B104M


AC Switching Characteristics

Parameters				Description	20 ns		25 ns		45 ns		Unit
Cypress	Alt			Description	Min	Max	Min	Max	Min	Max	Unit
Parameters	Parameters				Min	Max	Min	Max	Min	Max
Parameters	Parameters
SRAM Read Cycle
tACE	tACS			Chip Enable Access Time		20		25		45	ns
tRC [16]	tRC			Read Cycle Time	20		25		45		ns
tAA [17]	tAA			Address Access Time		20		25		45	ns
tDOE	tOE			Output Enable to Data Valid		10		12		20	ns
tOHA[17]	tOH			Output Hold After Address Change	3		3		3		ns
tLZCE [14, 18]	tLZ			Chip Enable to Output Active	3		3		3		ns
tHZCE [14, 18]	tHZ			Chip Disable to Output Inactive		8		10		15	ns
tLZOE [14, 18]	tOLZ			Output Enable to Output Active	0		0		0		ns
tHZOE [14, 18]	tOHZ			Output Disable to Output Inactive		8		10		15	ns
tPU [14]	tPA			Chip Enable to Power Active	0		0		0		ns
tPD [14]	tPS			Chip Disable to Power Standby		20		25		45	ns
tDBE	-			Byte Enable to Data Valid		10		12		20	ns
tLZBE[14]	-			Byte Enable to Output Active	0		0		0		ns
tHZBE[14]	-			Byte Disable to Output Inactive		8		10		15	ns
SRAM Write Cycle
tWC	tWC			Write Cycle Time	20		25		45		ns
tPWE	tWP			Write Pulse Width	15		20		30		ns
tSCE	tCW			Chip Enable To End of Write	15		20		30		ns
tSD	tDW			Data Setup to End of Write	8		10		15		ns
tHD	tDH			Data Hold After End of Write	0		0		0		ns
tAW	tAW			Address Setup to End of Write	15		20		30		ns
tSA	tAS			Address Setup to Start of Write	0		0		0		ns
tHA	tWR			Address Hold After End of Write	0		0		0		ns
tHZWE [14, 18,19]	tWZ			Write Enable to Output Disable		8		10		15	ns
tLZWE [14, 18]	tOW			Output Active after End of Write	3		3		3		ns
tBW	-			Byte Enable to End of Write	15		20		30		ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled[16, 17, 20]

	tRC
Address	Address Valid
	tAA
Data Output	Previous Data Valid
	tOHA

Notes

16.WE must be HIGH during SRAM read cycles.

17.Device is continuously selected with CE, OE and BHE / BLE LOW.

18.Measured ±200 mV from steady state output voltage.

19.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.

20.HSB must remain HIGH during READ and WRITE cycles.

Output Data Valid

Document #: 001-07103 Rev. *K

Page 17 of 31

[+] Feedback

Image 17

Cypress CY14B104K manual AC Switching Characteristics, Switching Waveforms, Parameters Sram Read Cycle, Sram Write Cycle

Contents

Cypress Semiconductor Corporation 198 Champion Court FeaturesFunctional Description Pinouts Sram Read Device OperationSram Write AutoStore Operation Hardware Store HSB Operation Hardware Recall Power UpSoftware Recall Software Store A15 A06 Mode Power Mode SelectionPreventing AutoStore Store Real Time Clock Operation Data ProtectionNoise Considerations Calibrating the Clock AlarmWatchdog Timer Interrupt Register Power MonitorInterrupts Flags Register PF Power Fail Flag WDF Watchdog Timer FlagPFE Power Fail Enable AF Alarm Flag WDF Oscf OscenWDS For the register is 0x7FFF9 0x3FFF9 Time Keeping Seconds Time-base 0x7FFF5 0x3FFF5 Alarm DayWatchdog Write only. Reading it always returns a Centuries 0x7FFF0 0x3FFF0 Flags 0x7FFF2 0x3FFF2 Alarm SecondsThis condition and write 0 to clear this flag Document # 001-07103 Rev. *K Range Ambient Temperature DC Electrical CharacteristicsMaximum Ratings Operating Range Capacitance Data Retention and EnduranceThermal Resistance AC Test Conditions Hot Temperature 85 oC RTC Backup CurrentRTC Battery Pin Voltage RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start Switching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write Cycle Standby Active Data Output High Impedance Output Data ValidAddress Valid Data Input Input Data Valid Input Data Valid High Impedance Data Input Data OutputNot applicable for RTC register writes Address Address Valid Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up Recall Software Controlled Store and Recall Cycle Hardware Store Cycle To Output Active Time when write latch not setDescription 20 ns 25 ns 45 ns Unit Min Hardware Store Pulse Width For x16 Configuration For x8 ConfigurationInputs and Outputs Mode Power Truth Table For Sram Operations Nvsram Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TZS Tsop Ordering Information Pin Tsop II Package Diagrams 51-85160 TUP Document HistoryPCI UHA GVCH/PYRS Footnote 1 and 8 referenced for Mode selection Table Added 20 ns access speed in Features6 updated Data protection description 6 Updated Starting and stopping the oscillator description USB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions