Cypress CY14B104K, CY14B104M - page 10

PRELIMINARY CY14B104K, CY14B104M

Document #: 001-07103 Rev. *K Page 10 of 31

Table 4. RTC Register Map[8]

Register BCD Format Data[9]

Function/Range

CY14B104K CY14B104M D7 D6 D5 D4 D3 D2 D1 D0

0x7FFFF 0x3FFFF 10s Years Years Years: 00–99

0x7FFFE 0x3FFFE 0 0 0 10s

Months

Months Months: 01–12

0x7FFFD 0x3FFFD 0 0 10s Day of Month Day Of Month Day of Month: 01–31

0x7FFFC 0x3FFFC 0 0 0 0 0 Day of week Day of week: 01–07

0x7FFFB 0x3FFFB 0 0 10s Hours Hours Hours: 00–23

0x7FFFA 0x3FFFA 0 10s Minutes Minutes Minutes: 00–59

0x7FFF9 0x3FFF9 0 10s Seconds Seconds Seconds: 00–59

0x7FFF8 0x3FFF8 OSCEN

(0)

0Cal Sign

(0)

Calibration (00000) Calibration Values [10]

0x7FFF7 0x3FFF7 WDS

(0)

WDW (0) WDT (000000) Watchdog [10]

0x7FFF6 0x3FFF6 WIE (0) AIE (0) PFE (0) 0 H/L

(1)

P/L (0) 0 0 Interrupts [10]

0x7FFF5 0x3FFF5 M (1) 0 10s Alarm Date Alarm Day Alarm, Day of Month:

01–31

0x7FFF4 0x3FFF4 M (1) 0 10s Alarm Hours Alarm Hours Alarm, Hours: 00–23

0x7FFF3 0x3FFF3 M (1) 10 Alarm Minutes Alarm Minutes Alarm, Minutes:

00–59

0x7FFF2 0x3FFF2 M (1) 10 Alarm Seconds Alarm, Seconds Al arm, Seconds:

00–59

0x7FFF1 0x3FFF1 10s Centuries Centuries Centuries: 00–99

0x7FFF0 0x3FFF0 WDF AF PF OSCF 0 CAL (0) W (0) R (0) Flags [10]

Note

8. Upper Byte D15-D8 (CY14B104MA) of RTC registers are reserved for future use

9. ( ) designates values shipped from the factory.

10.This is a binary value, not a BCD value.

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Contents

Main PRELIMINARY CY14B104K, CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock Features Real Time Clock 20 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14B104K) or 256K x 16 (CY14B104M) Pinouts Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II 44 - TSOP II Top View (not to scale) 54 - TSOP II Top View (not to scale) Device Operation SRAM Read SRAM Write AutoStore Operation PRELIMINARY CY14B104K, CY14B104M Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Software STORE Software RECALL Preventing AutoStore Data Protection Noise Considerations Real Time Clock Operation nvTIME Operation Clock Operations Calibrating the Clock Alarm Watchdog Timer Power Monitor Interrupts Interrupt Register Flags Register Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram X1 X2 V Enable Page Page Page Page PRELIMINARY CY14B104K, CY14B104M Maximum Ratings Operating Range DC Electrical Characteristics AC Test Conditions Data Retention and Endurance Capacitance Thermal Resistance Page AC Switching Characteristics Figure 8. SRAM Read Cycle 2: CE Controlled[3, 16, 20] Figure 9. SRAM Write Cycle 1: WE Controlled[3, 19, 20, 21] Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21] Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22] (Not applicable for RTC register writes) AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Figure 12. AutoStore or Power Up RECALL Software Controlled STORE and RECALL Cycle Figure 13. CE and OE Controlled Software STORE and RECALL Cycle[29] Figure 14. Autostore Enable and Disable Cycle Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Figure 15. Hardware STORE Cycle Figure 16. Soft Sequence Processing Write latch set Truth Table For SRAM Operations For x8 Configuration For x16 Configuration Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C T Ordering Information Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) TOPVIEW BOTTOMVIEW 51-85087 *A Page Document History Page Page Page PRELIMINARY CY14B104K, CY14B104M Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions