Data Input Data Output, Address Address Valid

PRELIMINARY	CY14B104K, CY14B104M

Switching Waveforms

Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21]

Address

BHE, BLE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22]
(Not applicable for RTC register writes)
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Note

22. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.

Document #: 001-07103 Rev. *K

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Cypress CY14B104K manual Data Input Data Output, Input Data Valid High Impedance, Not applicable for RTC register writes

Contents

Functional Description FeaturesCypress Semiconductor Corporation 198 Champion Court Pinouts AutoStore Operation Device OperationSram Read Sram Write Software Store Hardware Recall Power UpHardware Store HSB Operation Software Recall Store Mode SelectionA15 A06 Mode Power Preventing AutoStore Noise Considerations Data ProtectionReal Time Clock Operation Watchdog Timer AlarmCalibrating the Clock Flags Register Power MonitorInterrupt Register Interrupts AF Alarm Flag WDF Watchdog Timer FlagPF Power Fail Flag PFE Power Fail Enable WDS OscenWDF Oscf For the register is 0x7FFF9 0x3FFF9 Time Keeping Seconds Write only. Reading it always returns a 0x7FFF5 0x3FFF5 Alarm DayTime-base Watchdog Document # 001-07103 Rev. *K 0x7FFF2 0x3FFF2 Alarm SecondsCenturies 0x7FFF0 0x3FFF0 Flags This condition and write 0 to clear this flag Operating Range DC Electrical CharacteristicsRange Ambient Temperature Maximum Ratings AC Test Conditions Data Retention and EnduranceCapacitance Thermal Resistance RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start RTC Backup CurrentHot Temperature 85 oC RTC Battery Pin Voltage Sram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read Cycle Data Input Input Data Valid Data Output High Impedance Output Data ValidStandby Active Address Valid Address Address Valid Data Input Data OutputInput Data Valid High Impedance Not applicable for RTC register writes Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up Recall Software Controlled Store and Recall Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min Truth Table For Sram Operations For x8 ConfigurationFor x16 Configuration Inputs and Outputs Mode Power ZS Tsop Part Numbering Nomenclature CY14 B 104 K ZS P 20 X C TNvsram Ordering Information Pin Tsop II Package Diagrams 51-85160 UHA Document HistoryTUP PCI GVCH/PYRS 6 Updated Starting and stopping the oscillator description Added 20 ns access speed in FeaturesFootnote 1 and 8 referenced for Mode selection Table 6 updated Data protection description Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

Cypress CY14B104K Data Input Data Output, Input Data Valid High Impedance, Address Address Valid

Models: CY14B104K CY14B104M

Switching Waveforms

Figure 10. SRAM Write Cycle 2: CE Controlled[3, 19, 20, 21]

BHE, BLE

Data Input

Data Output

Address Valid

Input Data Valid

High Impedance

Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[6, 19, 20, 21, 22]

(Not applicable for RTC register writes)

Address

Address Valid

BHE, BLE

Data Input

Input Data Valid

High Impedance

Data Output