CY8C23433, CY8C23533
Table 6. Register Map Bank 0 Table: User Space | (continued) |
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Name | Addr (0,Hex) | Access | Name |
| Addr (0,Hex) |
| Access | Name |
| Addr (0,Hex) | Access | Name | Addr (0,Hex) | Access |
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| 3E |
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| 7E |
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| BE |
| CPU_SCR1 | FE | # |
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| 3F |
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| 7F |
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| BF |
| CPU_SCR0 | FF | # |
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Gray fields are reserved. | # Access | is bit specific. |
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Table 7. Register Map Bank 1 Table: Configuration Space |
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Name | Addr (1,Hex) | Access | Name |
| Addr (1,Hex) |
| Access | Name |
| Addr (1,Hex) | Access | Name | Addr (1,Hex) | Access |
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PRT0DM0 | 00 | RW |
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| 40 |
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| 80 |
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| C0 |
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PRT0DM1 | 01 | RW |
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| 41 |
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| 81 |
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| C1 |
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PRT0IC0 | 02 | RW |
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| 42 |
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| 82 |
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| C2 |
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PRT0IC1 | 03 | RW |
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| 43 |
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| 83 |
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| C3 |
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PRT1DM0 | 04 | RW |
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| 44 |
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| ASD11CR0 |
| 84 | RW |
| C4 |
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PRT1DM1 | 05 | RW |
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| 45 |
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| ASD11CR1 |
| 85 | RW |
| C5 |
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PRT1IC0 | 06 | RW |
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| 46 |
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| ASD11CR2 |
| 86 | RW |
| C6 |
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PRT1IC1 | 07 | RW |
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| 47 |
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| ASD11CR3 |
| 87 | RW |
| C7 |
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PRT2DM0 | 08 | RW |
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| 48 |
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| 88 |
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| C8 |
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PRT2DM1 | 09 | RW |
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| 49 |
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| 89 |
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| C9 |
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PRT2IC0 | 0A | RW |
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| 4A |
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| 8A |
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| CA |
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PRT2IC1 | 0B | RW |
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| 4B |
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| 8B |
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| CB |
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PRT3DM0 | 0C | RW |
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| 4C |
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| 8C |
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| CC |
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PRT3DM1 | 0D | RW |
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| 4D |
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| 8D |
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| CD |
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PRT3IC0 | 0E | RW |
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| 4E |
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| 8E |
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| CE |
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PRT3IC1 | 0F | RW |
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| 4F |
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| 8F |
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| CF |
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| 10 |
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| 50 |
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| 90 |
| GDI_O_IN | D0 | RW |
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| 11 |
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| 51 |
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| 91 |
| GDI_E_IN | D1 | RW |
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| 12 |
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| 52 |
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| 92 |
| GDI_O_OU | D2 | RW |
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| 13 |
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| 53 |
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| 93 |
| GDI_E_OU | D3 | RW |
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| 14 |
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| 54 |
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| ASC21CR0 |
| 94 | RW |
| D4 |
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| 15 |
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| 55 |
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| ASC21CR1 |
| 95 | RW |
| D5 |
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| 16 |
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| 56 |
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| ASC21CR2 |
| 96 | RW |
| D6 |
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| 17 |
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| 57 |
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| ASC21CR3 |
| 97 | RW |
| D7 |
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| 18 |
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| 58 |
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| 98 |
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| D8 |
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| 19 |
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| 59 |
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| 99 |
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| D9 |
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| 1A |
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| 5A |
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| 9A |
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| DA |
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| 1B |
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| 5B |
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| 9B |
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| DB |
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| 1C |
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| 5C |
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| 9C |
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| DC |
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| 1D |
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| 5D |
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| 9D |
| OSC_GO_EN | DD | RW |
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| 1E |
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| 5E |
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| 9E |
| OSC_CR4 | DE | RW |
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| 1F |
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| 5F |
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| 9F |
| OSC_CR3 | DF | RW |
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DBB00FN | 20 | RW | CLK_CR0 |
| 60 |
| RW |
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| A0 |
| OSC_CR0 | E0 | RW |
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DBB00IN | 21 | RW | CLK_CR1 |
| 61 |
| RW |
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| A1 |
| OSC_CR1 | E1 | RW |
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DBB00OU | 22 | RW | ABF_CR0 |
| 62 |
| RW |
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| A2 |
| OSC_CR2 | E2 | RW |
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| 23 |
| AMD_CR0 |
| 63 |
| RW |
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| A3 |
| VLT_CR | E3 | RW |
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DBB01FN | 24 | RW |
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| 64 |
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| A4 |
| VLT_CMP | E4 | R |
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DBB01IN | 25 | RW |
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| 65 |
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| A5 |
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| E5 |
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DBB01OU | 26 | RW | AMD_CR1 |
| 66 |
| RW |
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| A6 |
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| E6 |
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| 27 |
| ALT_CR0 |
| 67 |
| RW |
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| A7 |
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| E7 |
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DCB02FN | 28 | RW |
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| 68 |
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| SARADC_TRS |
| A8 | RW | IMO_TR | E8 | W |
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DCB02IN | 29 | RW |
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| 69 |
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| SARADC_TRCL |
| A9 | RW | ILO_TR | E9 | W |
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DCB02OU | 2A | RW |
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| 6A |
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| SARADC_TRCH |
| AA | RW | BDG_TR | EA | RW |
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| 2B |
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| 6B |
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| SARADC_CR2 |
| AB | # | ECO_TR | EB | W |
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DCB03FN | 2C | RW | TMP_DR0 |
| 6C |
| RW | SARADC_LCR |
| AC | RW |
| EC |
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DCB03IN | 2D | RW | TMP_DR1 |
| 6D |
| RW |
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| AD |
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| ED |
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DCB03OU | 2E | RW | TMP_DR2 |
| 6E |
| RW |
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| AE |
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| EE |
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| 2F |
| TMP_DR3 |
| 6F |
| RW |
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| AF |
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| EF |
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| 30 |
| ACB00CR3 |
| 70 |
| RW | RDI0RI |
| B0 | RW |
| F0 |
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| 31 |
| ACB00CR0 |
| 71 |
| RW | RDI0SYN |
| B1 | RW |
| F1 |
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| 32 |
| ACB00CR1 |
| 72 |
| RW | RDI0IS |
| B2 | RW |
| F2 |
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| 33 |
| ACB00CR2 |
| 73 |
| RW | RDI0LT0 |
| B3 | RW |
| F3 |
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| 34 |
| ACB01CR3 |
| 74 |
| RW | RDI0LT1 |
| B4 | RW |
| F4 |
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Gray fields are reserved. | # Access is bit specific. |
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Document Number: |
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| Page 12 of 37 | |||||
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