CY8C23433, CY8C23533
AC Low Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
Table 28. AC Low Power Comparator Specifications
Symbol | Description | Min | Typ | Max | Units | Notes |
TRLPC | LPC response time | – | – | 50 | μs | ≥ 50 mV overdrive comparator |
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| reference set within VREFLPC |
AC Digital Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
Table 29. 5V and 3.3V AC Digital Block Specifications
Symbol | Description | Min | Typ | Max | Units | Notes |
Timer | Capture Pulse Width | 50[17] | – | – | ns |
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| Maximum Frequency, No Capture | – | – | 49.2 | MHz | 4.75V < Vdd < 5.25V |
| Maximum Frequency, With Capture | – | – | 24.6 | MHz |
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Counter | Enable Pulse Width | 50[17] | – | – | ns |
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| Maximum Frequency, No Enable Input | – | – | 49.2 | MHz | 4.75V < Vdd < 5.25V |
| Maximum Frequency, Enable Input | – | – | 24.6 | MHz |
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Dead Band | Kill Pulse Width: |
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| Asynchronous Restart Mode | 20 | – | – | ns |
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| Synchronous Restart Mode | 50[17] | – | – | ns |
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| Disable Mode | 50[17] | – | – | ns |
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| Maximum Frequency | – | – | 49.2 | MHz | 4.75V < Vdd < 5.25V |
CRCPRS | Maximum Input Clock Frequency | – | – | 49.2 | MHz | 4.75V < Vdd < 5.25V |
(PRS |
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Mode) |
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CRCPRS | Maximum Input Clock Frequency | – | – | 24.6 | MHz |
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(CRC |
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Mode) |
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SPIM | Maximum Input Clock Frequency | – | – | 8.2 | MHz | Maximum data rate at 4.1 MHz due |
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| to 2 x over clocking. |
SPIS | Maximum Input Clock Frequency | – | – | 4.1 | MHz |
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| Width of SS_ Negated Between | 50[17] | – | – | ns |
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| Transmissions |
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Transmitter | Maximum Input Clock Frequency | – | – | 24.6 | MHz | Maximum data rate at 3.08 MHz due |
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| to 8 x over clocking. |
| Maximum Input Clock Frequency with Vdd ≥ | – | – | 49.2 | MHz | Maximum data rate at 6.15 MHz due |
| 4.75V, 2 Stop Bits |
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| to 8 x over clocking. |
Receiver | Maximum Input Clock Frequency | – | – | 24.6 | MHz | Maximum data rate at 3.08 MHz due |
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| to 8 x over clocking. |
| Maximum Input Clock Frequency with Vdd ≥ | – | – | 49.2 | MHz | Maximum data rate at 6.15 MHz due |
| 4.75V, 2 Stop Bits |
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| to 8 x over clocking. |
Note
17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: | Page 30 of 37 |
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