CY8C23433, CY8C23533
AC External Clock Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
Table 32. 5V AC External Clock Specifications
Symbol | Description | Min | Typ | Max | Units | |
FOSCEXT | Frequency | 0.093 | – | 24.6 | MHz | |
– | High Period | 20.6 | – | 5300 | ns | |
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– | Low Period | 20.6 | – | – | ns | |
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– | Power Up IMO to Switch | 150 | – | – | μs | |
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Table 33. 3.3V AC External Clock Specifications |
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| Description | Min | Typ | Max | Units |
FOSCEXT | Frequency with CPU Clock divide by 1[18] | 0.093 | – | 12.3 | MHz | |
FOSCEXT | Frequency with CPU Clock divide by 2 or greater[19] | 0.186 | – | 24.6 | MHz | |
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| High Period with CPU Clock divide by 1 | 41.7 | – | 5300 | ns |
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| Low Period with CPU Clock divide by 1 | 41.7 | – | – | ns |
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| Power Up IMO to Switch | 150 | – | – | μs |
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AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
Table 34. AC Programming Specifications
Symbol | Description | Min | Typ | Max | Units | Notes |
TRSCLK | Rise Time of SCLK | 1 | – | 20 | ns |
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TFSCLK | Fall Time of SCLK | 1 | – | 20 | ns |
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TSSCLK | Data Set up Time to Falling Edge of SCLK | 40 | – | – | ns |
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THSCLK | Data Hold Time from Falling Edge of SCLK | 40 | – | – | ns |
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FSCLK | Frequency of SCLK | 0 | – | 8 | MHz |
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TERASEB | Flash Erase Time (Block) | – | 20 | – | ms |
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TWRITE | Flash Block Write Time | – | 20 | – | ms |
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TDSCLK | Data Out Delay from Falling Edge of SCLK | – | – | 45 | ns | Vdd > 3.6 |
TDSCLK3 | Data Out Delay from Falling Edge of SCLK | – | – | 50 | ns | 3.0 ≤ Vdd ≤ 3.6 |
SAR8 ADC AC Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and
Table 35. SAR8 ADC AC Specifications[20]
Symbol | Description | Min | Typ | Max | Units |
Freq3 | Input clock frequency 3V | – | – | 3.075 | MHz |
Freq5 | Input clock frequency 5V | – | – | 3.075 | MHz |
Notes
18.Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
19.If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.
20.The max sample rate in this R2R ADC is 3.0/8=375KSPS
Document Number: | Page 32 of 37 |
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