Cypress CY8C23433, CY8C23533 manual AC I2C Specifications

CY8C23433, CY8C23533

AC I2C Specifications

The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only.

Table 36. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V

Symbol	Description	Standard Mode		Fast Mode		Units
		Min	Max	Min	Max
FSCLI2C	SCL Clock Frequency	0	100	0	400	kHz
THDSTAI2C	Hold Time (repeated) START Condition. After this period, the	4.0	–	0.6	–	μs
	first clock pulse is generated.
TLOWI2C	LOW Period of the SCL Clock	4.7	–	1.3	–	μs
THIGHI2C	HIGH Period of the SCL Clock	4.0	–	0.6	–	μs
TSUSTAI2C	Setup Time for a Repeated START Condition	4.7	–	0.6	–	μs
THDDATI2C	Data Hold Time	0	–	0	–	μs
TSUDATI2C	Data Setup Time	250	–	100[21]	–	ns
TSUSTOI2C	Setup Time for STOP Condition	4.0	–	0.6	–	μs
TBUFI2C	Bus Free Time Between a STOP and START Condition	4.7	–	1.3	–	μs
TSPI2C	Pulse Width of spikes are suppressed by the input filter.	–	–	0	50	ns

Table 37. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)

Symbol	Description	Standard Mode		Fast Mode		Units
		Min	Max	Min	Max
FSCLI2C	SCL Clock Frequency	0	100	–	–	kHz
THDSTAI2C	Hold Time (repeated) START Condition. After this period, the	4.0	–	–	–	μs
	first clock pulse is generated.
TLOWI2C	LOW Period of the SCL Clock	4.7	–	–	–	μs
THIGHI2C	HIGH Period of the SCL Clock	4.0	–	–	–	μs
TSUSTAI2C	Setup Time for a Repeated START Condition	4.7	–	–	–	μs
THDDATI2C	Data Hold Time	0	–	–	–	μs
TSUDATI2C	Data Setup Time	250	–	–	–	ns
TSUSTOI2C	Setup Time for STOP Condition	4.0	–	–	–	μs
TBUFI2C	Bus Free Time Between a STOP and START Condition	4.7	–	–	–	μs
TSPI2C	Pulse Width of spikes are suppressed by the input filter.	–	–	–	–	ns

Figure 17. Definition for Timing for Fast/Standard Mode on the I2C Bus

SDA	TLOWI2C
		TSUDATI2C
SCL
S	THDSTAI2C THDDATI2C	THIGHI2C	TSUSTAI2C

THDSTAI2C

Sr

TSPI2C		TBUFI2C
TSUSTOI2C	P	S

Note

21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

Figure 18.

SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

Document Number: 001-44369 Rev. *B Page 33 of 37

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