CYV15G0404RB
Figure 1. HOTLink II™ System Connections
Video Coprocessor
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Independent
Channel
CYV15G0403TB
Serializer
Reclocked
Outputs
Serial Links
Reclocked
Outputs 
Independent
Channel
CYV15G0404RB
Reclocking Deserializer
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Video Coprocessor
CYV15G0404RB Deserializing Reclocker Logic Block Diagram
| RXDA[9:0] |
| TRGCLKA± | |
| x10 |
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| RXDB[9:0] |
| TRGCLKB± | |
| x10 |
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| RXDC[9:0] |
| TRGCLKC± | |
| x10 |
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| RXDD[9:0] |
| TRGCLKD± | |
| x10 |
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Deserializer
Reclocker 
RX
Deserializer
Reclocker 
RX
Deserializer
Reclocker 
RX
Deserializer
Reclocker 
RX
ROUTA1± ROUTA2± | INA1± INA2± | ROUTB1± ROUTB2± | INB1± INB2± | ROUTC1± ROUTC2± | INC1± INC2± | ROUTD1± ROUTD2± | IND1± IND2± |
Document #: | Page 2 of 27 |
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