
CYV15G0404RB
Device Configuration and Control Block Diagram | = Internal Signal | 
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WREN ADDR[3:0] DATA[7:0]
Device Configuration and Control Interface
RXBIST[A..D]
RXRATE[A..D] SDASEL[A..D][1:0] RXPLLPD[A..D]
ROE[2..1][A..D] GLEN[11..0] FGLEN[2..0]
Document #:   | Page 5 of 27  | 
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