Receive Interface Read Timing RXRATEx = | Cypress CYV15G0404RB

CYV15G0404RB

Switching Waveforms for the CYV15G0404RB HOTLink II Receiver

Receive Interface

Read Timing

RXRATEx = 0

RXCLKx+

RXCLKx–

RXDx[9:0]

Receive Interface

Read Timing

RXRATEx = 1

RXCLKx+

RXCLKx–

RXDx[9:0]

tRXCLKP

tRXDV–

tRXDV+

tRXCLKP

tRXDV–

tRXDV+

CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms

Bus Configuration
Write Timing
ADDR[3:0]
DATA[7:0]
WREN	tDATAS

tWRENP

tDATAH

Document #: 38-02102 Rev. *C

Page 23 of 27

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Cypress CYV15G0404RB manual Receive Interface Read Timing RXRATEx =, Bus Configuration Write Timing

Contents

Cypress Semiconductor Corporation FeaturesFunctional Description CYV15G0404RB Deserializing Reclocker Logic Block Diagram Reclocking Deserializer Path Block Diagram Clock = Internal Signal Device Configuration and Control Block Diagram Pin Configuration Top View1 Pin Configuration Bottom View1 Asynchronous Device Reset Receive Path Clock SignalsDevice Control Signals Control Write Enable . Name IO Characteristics Signal DescriptionLink Fault Indication Output Device Configuration and Control Bus Signals Receive Bist Disabled Internal Device Configuration LatchesSignal Detect Amplitude Select Receive Channel Power Control CYV15G0404RB Receive Data Path CYV15G0404RB HOTLink II Operation Reclocker Clock/Data RecoveryLOW High Device Configuration and Control Interface Power Control Static Latch Values Force Global Enable FunctionMask Function Latch Types Device Configuration Strategy DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Device Control Latch Configuration Table Level Select Inputs Jtag SupportReceive Bist Status Bits Bistdatacompare 000 RX PLLBiststart Bistwait Maximum Ratings CYV15G0404RB DC Electrical Characteristics Operating Range AC Test Loads and Waveforms CYV15G0404RB DC Electrical Characteristics CYV15G0404RB AC Electrical Characteristics Parameter Description Test Conditions Max Unit PLL CharacteristicsCapacitance14 Parameter Description Min Max Unit CYV15G0404RB Device Receive Interface Read Timing RXRATEx = Bus Configuration Write Timing CML OUT VCC PowerCML Lvttl in PU TMS Lvttl in PU ROUTB2+ CML OUTTDI Lvttl in PU RXDB8 Lvttl OUT Range Package DiagramOrdering Information Speed Ordering Code Package Package Type Operating AGT Document HistoryFRE SUA