Cypress CYV15G0404RB manual Device Control Latch Configuration Table

CYV15G0404RB

Table 4. Device Control Latch Configuration Table

ADDR	Channel	Type	DATA7	DATA6	DATA5	DATA4	DATA3	DATA2	DATA1	DATA0	Reset
											Value
0	A	S	1	0	X	X	0	0	RXRATEA	GLEN0	10111111
(0000b)
1	A	S	SDASEL2A[1]	SDASEL2A[0]	SDASEL1A[1]	SDASEL1A[0]	X	X	TRGRATEA	GLEN1	10101101
(0001b)
2	A	D	RXBISTA[1]	RXPLLPDA	RXBISTA[0]	X	ROE2A	ROE1A	X	GLEN2	10110011
(0010b)
3	B	S	1	0	X	X	0	0	RXRATEB	GLEN3	10111111
(0011b)
4	B	S	SDASEL2B[1]	SDASEL2B[0]	SDASEL1B[1]	SDASEL1B[0]	X	X	TRGRATEB	GLEN4	10101101
(0100b)
5	B	D	RXBISTB[1]	RXPLLPDB	RXBISTB[0]	X	ROE2B	ROE1B	X	GLEN5	10110011
(0101b)
6	C	S	1	0	X	X	0	0	RXRATEC	GLEN6	10111111
(0110b)
7	C	S	SDASEL2C[1]	SDASEL2C[0]	SDASEL1C[1]	SDASEL1C[0]	X	X	TRGRATEC	GLEN7	10101101
(0111b)
8	C	D	RXBISTC[1]	RXPLLPDC	RXBISTC[0]	X	ROE2C	ROE1C	X	GLEN8	10110011
(1000b)
9	D	S	1	0	X	X	0	0	RXRATED	GLEN9	10111111
(1001b)
10	D	S	SDASEL2D[1]	SDASEL2D[0]	SDASEL1D[1]	SDASEL1D[0]	X	X	TRGRATED	GLEN10	10101101
(1010b)
11	D	D	RXBISTD[1]	RXPLLPDD	RXBISTD[0]	X	ROE2D	ROE1D	X	GLEN11	10110011
(1011b)
12	GLOBAL	S	1	0	X	X	0	0	RXRATEGL	FGLEN0	N/A
(1100b)
13	GLOBAL	S	SDASEL2GL[1]	SDASEL2GL[0]	SDASEL1GL[1]	SDASEL1GL[0]	X	X	TRGRATEGL	FGLEN1	N/A
(1101b)
14	GLOBAL	D	RXBISTGL[1]	RXPLLPDGL	RXBISTGL[0]	X	ROE2GL	ROE1GL	X	FGLEN2	N/A
(1110b)
15	MASK	D	D7	D6	D5	D4	D3	D2	D1	D0	11111111
(1111b)

Document #: 38-02102 Rev. *C Page 16 of 27

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