CYV15G0404RB
JTAG Support
The CYV15G0404RB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the TRGCLKx± clock input. The
To ensure valid device operation after
Table 5. Receive BIST Status Bits
JTAG controller does not enter any of the test modes after device
Note The order of device reset (using RESET) and JTAG initialization does not matter.
3-Level Select Inputs
Each
JTAG ID
The JTAG device ID for the CYV15G0404RB is ‘0C811069’x.
{BISTSTx, RXDx[0], | Description | |
Receive BIST Status | ||
RXDx[1]} | ||
| (Receive BIST = Enabled) | |
000, 001 | BIST Data Compare. Character compared correctly. | |
010 | BIST Last Good. Last Character of BIST sequence detected and valid. | |
|
| |
011 | Reserved. | |
|
| |
100 | BIST Last Bad. Last Character of BIST sequence detected invalid. | |
101 | BIST Start. Receive BIST is enabled on this channel, but character compares have not yet | |
| commenced. This also indicates a PLL Out of Lock condition. | |
110 | BIST Error. While comparing characters, a mismatch was found in one or more of the character bits. | |
|
| |
111 | BIST Wait. The receiver is comparing characters, but has not yet found the start of BIST character to | |
| enable the LFSR. |
Document #: | Page 17 of 27 |
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