CYV15G0404RB
CYV15G0404RB DC Electrical Characteristics (continued)
Parameter |
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| Test Conditions |
| Min |
| Max | Unit | |||||||||||||
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Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±, ROUTD2± | |||||||||||||||||||||||||
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VOHC | Output HIGH Voltage |
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| 100Ω differential load |
| VCC – 0.5 |
| VCC – 0.2 | V | |||||||||||||||
| (VCC Referenced) |
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| 150Ω differential load |
| VCC – 0.5 |
| VCC – 0.2 | V | ||||||||||||||||
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VOLC | Output LOW Voltage |
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| 100Ω differential load |
| VCC – 1.4 |
| VCC – 0.7 | V | |||||||||||||||
| (VCC Referenced) |
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| 150Ω differential load |
| VCC – 1.4 |
| VCC – 0.7 | V | ||||||||||||||||
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VODIF | Output Differential Voltage |
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| 100Ω differential load |
| 450 |
| 900 | mV | |||||||||||||||
| (OUT+) − (OUT−) |
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| 150Ω differential load |
| 560 |
| 1000 | mV | ||||||||||||||||
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Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2± |
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VDIFFs[7] | Input Differential Voltage (IN+) − (IN−) |
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| 100 |
| 1200 | mV | |||||||||||||||
VIHE | Highest Input HIGH Voltage |
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| VCC | V | |||||||||||
VILE | Lowest Input LOW Voltage |
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| VCC – 2.0 |
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IIHE | Input HIGH Current |
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| VIN = VIHE Max. |
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| 1350 | µA | ||||||||||||||
IILE | Input LOW Current |
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| VIN = VILE Min. |
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VICOM[9] | Common Mode input range |
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| ((VCC – 2.0V)+0.5)min, |
| +1.25 |
| +3.1 | V | |||||||||||||||
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| (VCC | – 0.5V) max. |
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Power Supply |
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| Max |
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ICC [10,11] | Max Power Supply Current |
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| TRGCLKx= | Commercial |
| 910 |
| 1270 | mA | ||||||||||||||
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| MAX |
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| Industrial |
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| 1320 | mA | ||
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ICC [10,11] | Typical Power Supply Current |
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| TRGCLKx= | Commercial |
| 900 |
| 1270 | mA | ||||||||||||||
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| 125 MHz |
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| Industrial |
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| 1320 | mA | |||
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AC Test Loads and Waveforms |
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| 3.3V |
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| R1 = 590Ω |
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| R1 |
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| RL = 100Ω |
| RL |
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| (Includes fixture and |
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| R2 = 435Ω | CL |
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| CL ≤ 7 pF |
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| R2 |
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| (Includes fixture and |
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| (b) CML Output Test Load | [12] |
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| probe capacitance) |
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(a) LVTTL Output Test Load[12]
Vth = 1.4V
GND
≤ 1 ns 
3.0V
2.0V 2.0V
0.8V 0.8V
VIHE
Vth = 1.4V
20%
VILE
≤ 1 ns | ≤ 270 ps |
VIHE
80%80%
VILE
20%
≤ 270 ps
(c) LVTTL Input Test Waveform[13] | (d) CML/LVPECL Input Test Waveform |
Notes
9.The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero crossing between the true and complement inputs as the signal switches between a
10.Maximum ICC is measured with VCC = MAX, TA = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded.
11.Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C, with all channels enabled and one Serial Line Driver for each transmit channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
12.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
Document #: | Page 20 of 27 |
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