Cypress CYV15G0404RB manual Clock

CYV15G0404RB

Reclocking Deserializer Path Block Diagram (continued) = Internal Signal

TRGRATEC

TRGCLKC x2

SDASEL[2..1]C[1:0]

LDTDEN

	Receive
INSELC	Signal				LFSRBIST
	Monitor		Shifter
				10		10
INC2+	Data
INC1+
INC1–	Clock &
INC2–	Recovery
ULCC	PLL
SPDSELC			RXBISTC[1:0]
RXPLLPDC
				RXRATEC
	Recovered Character Clock	Recovered Serial Data
	Reclocker			ROE[2..1]C
	Output PLL
	Clock Multiplier C
RECLKOC	Character-Rate Clock C
REPDOC

Output Register

Register

			LFIC
		RXDC[9:0]
10
		BISTSTC
		RXCLKC+
	⎟2
RXCLKC–

ROE[2..1]C

ROUTC1+

ROUTC1–

ROUTC2+

ROUTC2–

TRGRATED

TRGCLKD x2

SDASEL[2..1]D[1:0]

LDTDEN

	Receive
INSELD	Signal				LFSRBIST
	Monitor		Shifter
				10		10
IND2+	Data
IND1+
IND1–	Clock &
IND2–	Recovery
ULCD	PLL
SPDSELD			RXBISTD[1:0]
RXPLLPDD
				RXRATED
	Recovered Character Clock	Recovered Serial Data
	Reclocker			ROE[2..1]D
	Output PLL
	Clock Multiplier D
RECLKOD	Character-Rate Clock D
REPDOD

Output Register

Register

			LFID
		RXDD[9:0]
10
		BISTSTD
		RXCLKD+
	⎟2
RXCLKD–

ROE[2..1]D

ROUTD1+

ROUTD1–

ROUTD2+

ROUTD2–

Document #: 38-02102 Rev. *C Page 4 of 27

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