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Cypress CYV15G0404RB manual Document History Page, Document Number, Ecn No, Issue, Orig. Of, Date

Models: CYV15G0404RB

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CYV15G0404RB

Document History Page

Document Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker

Document Number: 38-02102

REV.	ECN NO.	ISSUE	ORIG. OF	DESCRIPTION OF CHANGE
REV.	ECN NO.	DATE	CHANGE	DESCRIPTION OF CHANGE
		DATE	CHANGE

**	246850	See ECN	FRE	New Data Sheet

*A	338721	See ECN	SUA	Added Pb-Free package option availability

*B	384307	See ECN	AGT	Revised setup and hold times (tRXDv–, tRXDv+)
*C	789283	See ECN	KKVTMP	Clarification to the need and procedure to initialize the JTAG controller
				(during test and non-test mode) to ensure valid device power-up. No
				changes have been made to the device specifications or character-
				estics.

Document #: 38-02102 Rev. *C

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Cypress CYV15G0404RB manual Document History Page, Document Number, Ecn No, Issue, Orig. Of, Description Of Change, Date

Contents

Independent Clock Quad HOTLink II Deserializing Reclocker FeaturesCYV15G0404RB Functional DescriptionReclocker RX CYV15G0404RB Deserializing Reclocker Logic Block DiagramCYV15G0404RB Reclocker RXBoundary Reclocking Deserializer Path Block DiagramCYV15G0404RB JTAGCYV15G0404RB Reclocking Deserializer Path Block Diagram continued+ Feedback Device Configuration and Control Block Diagram= Internal Signal CYV15G0404RBPin Configuration Top View1 CYV15G0404RBPage 6 of Pin Configuration Bottom View1 CYV15G0404RBDocument # 38-02102 Rev. *C Receive Path Data and Status Signals Pin Definitions CYV15G0404RB Quad HOTLink II Deserializing ReclockerIO Characteristics Signal DescriptionPin Definitions continued CYV15G0404RB Quad HOTLink II Deserializing ReclockerCYV15G0404RB Page 10 of CYV15G0404RBPin Definitions continued CYV15G0404RB Quad HOTLink II Deserializing ReclockerTransition Density CYV15G0404RB HOTLink II OperationCYV15G0404RB Receive Data Path Analog AmplitudeCYV15G0404RB Receive Channel EnabledReclocker Output Channels Enabled Table 2. Operating Speed SettingsDevice Reset State Power ControlDevice Configuration and Control Interface BIST Status State MachinePage 14 of CYV15G0404RBPage 15 of CYV15G0404RBADDR ResetCYV15G0404RB + FeedbackTable 5. Receive BIST Status Bits JTAG SupportReceive BIST = Enabled CYV15G0404RBFigure 2. Receive BIST State Machine CYV15G0404RBCYV15G0404RB CYV15G0404RB DC Electrical CharacteristicsMaximum Ratings Operating RangeCYV15G0404RB DC Electrical Characteristics continued AC Test Loads and WaveformsCYV15G0404RB CYV15G0404RB CYV15G0404RB AC Electrical CharacteristicsCYV15G0404RB CYV15G0404RB AC Electrical Characteristics continuedPLL Characteristics Capacitance14ADDR30 Switching Waveforms for the CYV15G0404RB HOTLink II ReceiverCYV15G0404RB HOTLink II Bus Configuration Switching Waveforms CYV15G0404RBCYV15G0404RB CYV15G0404RB TOP VIEW Package DiagramOrdering Information CYV15G0404RBDocument Number Document History PageISSUE CYV15G0404RB

Document History Page

Document Number: 38-02102

ECN NO.

ISSUE

ORIG. OF

DESCRIPTION OF CHANGE

DATE

CHANGE