Envision Peripherals NV3128 manual Asynchronous Timing, Partitioning, Power Regulation

ASYNCHRONOUS TIMING

Asynchronous system timing consists of two signals. The first, derived from the reference video input’s re-trace interval, activates the pre-loaded informationinthecrosspoint’sdouble-bufferedregisters.Thisactionexecutes a take. The second timing signal is a system master clock.

A sync stripper derives the vertical retrace pulse and passes it on to a microprocessor for processing into strobe and write-enable signals.

An oscillator provides the master clock for the entire system. When used on the NV3128, this oscillator free runs.

PARTITIONING

On the Command Interpretertwobanks of DIP switches and theirassociated circuitryconfiguretheNV3128intopartitions.Additionally,softwareversions supporting various controllers may make use of these switches for supplementaryconfigurationcontrol.

On the newer Universal Control module, partitioning is set up using UniDiag and stored in memory.

PARALLEL INTERFACE (COMMAND INTERPRETER ONLY)

Line driver/receivers interface with the parallel RS-422A circuits that characterize the PESAprotocol interface. Aprogrammable gate array and matrixSRAMworkinconjunctiontogatherandprocessthisveryhighspeed data.

POWER REGULATION

Power regulator circuitry regulates the incoming raw DC voltage from the PS2001 power supply to +/-15VDC and +/-5VDC respectively.

NV3128 RS-422A Machine-Control Data Routing Switch 4-9