Instruction List (2) S1C6200 Core CPU
Opcode
PSET
JP
JPBA
CALL
CALZ
RET
RETS
RETD
NOP5
NOP7
HALT
SLP
INC
LD
ADC
Clasiffication
Branch
instructions
System
control
instructions
Index
operation
instructions
Operand
p
s
C, s
NC, s
Z, s
NZ, s
s
s
l
X
Y
X, x
Y, y
XP, r
XH, r
XL, r
YP, r
YH, r
YL, r
r, XP
r, XH
r, XL
r, YP
r, YH
r, YL
XH, i
XL, i
YH, i
YL, i
Function
NPBp[4], NPPp[3:0]
PCBNBP, PCPNPP, PCSs
PCBNBP, PCPNPP, PCSs, if C=1
PCBNBP, PCPNPP, PCSs, if C=0
PCBNBP, PCPNPP, PCSs, if Z=1
PCBNBP, PCPNPP, PCSs, if Z=0
PCBNBP, PCPNPP, PCSHB, PCSLA
M(SP-1)PCP, M(SP-2)PCSH, M(SP-3)PCSL+1, SPSP-3, PCPNPP, PCSs
M(SP-1)PCP, M(SP-2)PCSH, M(SP-3)PCSL+1, SPSP-3, PCP0, PCSs
PCSLM(SP), PCSHM(SP+1), PCPM(SP+2), SPSP+3
PCSLM(SP), PCSHM(SP+1), PCPM(SP+2), SPSP+3, PCPC+1
PCSLM(SP), PCSHM(SP+1), PCPM(SP+2), SPSP+3, M(X)l[3:0], M(X+1)l[7:4], XX+2
No operation (5 clock cycles)
No operation (7 clock cycles)
Halt (stop CPU)
Sleep (stop CPU and oscillation)
XX+1
YY+1
XHx[7:4], XLx[3:0]
YHy[7:4], YLy[3:0]
XPr
XHr
XLr
YPr
YHr
YLr
rXP
rXH
rXL
rYP
rYH
rYL
XHXH+i+C
XLXL+i+C
YHYH+i+C
YLYL+i+C
Clk
5
5
5
5
5
5
5
7
7
7
12
12
5
7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
1
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Z
C
I
D
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
0
Code
MSB LSB
Mnemonic Flags
Remarks
p
s
s
s
s
s
s
s
l
x
yr
r
r
r
r
r
r
r
r
r
r
r
i
i
i
i