Instruction List (4) S1C6200 Core CPU
Opcode
POP
LD
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
FAN
RLC
RRC
INC
DEC
ACPX
ACPY
SCPX
SCPY
NOT
Clasiffication
Stack
operation
instructions
Arithmetic
operation
instructions
Operand
XP
XH
XL
YP
YH
YL
F
SPH, r
SPL, r
r, SPH
r, SPL
r, i
r, q
r, i
r, q
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r
r
Mn
Mn
MX, r
MY, r
MX, r
MY, r
r
Function
XPM(SP), SPSP+1
XHM(SP), SPSP+1
XLM(SP), SPSP+1
YPM(SP), SPSP+1
YHM(SP), SPSP+1
YLM(SP), SPSP+1
FM(SP), SPSP+1
SPHr
SPLr
rSPH
rSPL
rr+i
rr+q
rr+i+C
rr+q+C
rr-q
rr-i-C
rr-q-C
rr & i
rr & q
rr | i
rr | q
rr ^ i
rr ^ q
r-i
r-q
r & i
r & q
d3d2, d2d1, d1d0, d0C, Cd3
d3C, d2d3, d1d2, d0d1, Cd0
M(n)M(n)+1
M(n)M(n)-1
M(X)M(X)+r+C, XX+1
M(Y)M(Y)+r+C, YY+1
M(X)M(X)-r-C, XX-1
M(Y)M(Y)-r-C, YY-1
r!r
Clk
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
Z
C
I
D
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code
MSB LSB
Mnemonic Flags
Remarks
iq
r
r
r
r
r
rriq
r
riq
r
riq
r
riq
r
riq
r
riq
r
ri
n
n
q
r
rr
r
r
r
r
r
r
q
r