Contents
xii C141-E057-01EN
5.5.2 Phases of operation 5-81
5.5.2.1 Ultra DMA burst initiation phase 5-81
5.5.2.2 Data transfer phase 5-82
5.5.2.3 Ultra DMA burst termination phase 5-82
5.5.3 Ultra DMA data in commands 5-83
5.5.3.1 Initiating an Ultra DMA data in burst 5-83
5.5.3.2 The data in transfer 5-84
5.5.3.3 Pausing an Ultra DMA data in burst 5-84
5.5.3.4 Terminating an Ultra DMA data in burst 5-85
5.5.4 Ultra DMA data out commands 5-88
5.5.4.1 Initiating an Ultra DMA data out burst 5-88
5.5.4.2 The data out transfer 5-88
5.5.4.3 Pausing an Ultra DMA data out burst 5-89
5.5.4.4 Terminating an Ultra DMA data out burst 5-90
5.5.5 Ultra DMA CRC rules 5-92
5.5.6 Series termination required for Ultra DMA 5-94
5.6 Timing 5-95
5.6.1 PIO data transfer 5-95
5.6.2 Single word DMA data transfer 5-97
5.6.3 Multiword DMA data transfer 5-98
5.6.4 Transfer of Ultra DMA data 5-99
5.6.4.1 Starting of Ultra DMA data In Burst 5-99
5.6.4.2 Ultra DMA data burst timing requirements 5-100
5.6.4.3 Sustained Ultra DMA data in burst 5-102
5.6.4.4 Host pausing an Ultra DMA data in burst 5-103
5.6.4.5 Device terminating an Ultra DMA data in burst 5-104
5.6.4.6 Host terminating an Ultra DMA data in burst 5-105
5.6.4.7 Initiating an Ultra DMA data out burst 5-106
5.6.4.8 Sustained Ultra DMA data out burst 5-107
5.6.4.9 Device pausing an Ultra DMA data out burst 5-108
5.6.4.10Host terminating an Ultra DMA data out burst 5-109
5.6.4.11Device terminating an Ultra DMA data in burst 5-110
5.6.5 Power-on and reset 5-111