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Fujitsu MHV2080AT System Configuration, ATA interface, 2 1 drive connection, Read/write circuit

Models: MHV2040AT MHV2100AT MHV2060AT MHV2080AT MHV2120AT

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2.2 System Configuration

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The high- speed microprocessor unit (MPU) achieves a high-performance AT controller.

2.2 System Configuration

2.2.1 ATA interface

Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100 MB/s).

2.2.2 1 drive connection

MHV2120AT

MHV2100AT

MHC2032AT

MHV2080AT

MHC2040AT

MHV2060AT

MHV2040AT

Figure 2.2 1 drive system configuration

C141-E218

2-3

Image 41

Fujitsu MHV2080AT manual System Configuration, ATA interface, 2 1 drive connection, Read/write circuit, Controller circuit

Contents

Disk Drive Product Manual MHV2120AT, MHV2100AT, MHV2080AT MHV2060AT, MHV2040AT Handling of This Manual For Safe Operation Revision History This page is intentionally left blank Overview of Manual Preface Conventions Conventions for Alert MessagesOperating Environment Liability Exception This page is intentionally left blank Damage Interface cable connection Important Alert ItemsImportant Alert Messages This page is intentionally left blank Disk Drive Product Manual Disk Drive Maintenance ManualManual Organization This page is intentionally left blank Contents Theory of Device Operation Installation Conditions Interface Contents 101 Write Multiple EXT X’39’ Option customizing Operations Glossary GL-1 Acronyms and Abbreviations AB-1 Index IN-1 Figures Illustrations Execution example of Read Multiple command Tables Surface temperature measurement points and standard 25 Relationship between combination of Identifier This page is intentionally left blank Device Overview Adaptability FeaturesFunctions and performance High resistance against shock Error correction and retry by ECCConnection to ATA interface Data buffer Specifications 1 Device SpecificationsSpecifications summary Examples of model names and product numbers Specifications 2Model and product number Ripple Power RequirementsInput Voltage Current and power dissipation Current Requirements and Power Dissipation Current fluctuation Typ. at +5 V when power is turned on Environmental SpecificationsPower on/off sequence Environmental specifications Shock and vibration specification Acoustic noise specificationAcoustic Noise Shock and Vibration Data assurance in the event of power failure Service lifeReliability Mean time between failures Mtbf Unrecoverable read error Error RatePositioning error Media Defects Advanced Power Management Advanced Power Management Advanced Power Management This page is intentionally left blank Device Configuration Device Configuration ATA interface System Configuration2 1 drive connection Read/write circuit 3 2 drives connection 2 drives configuration Installation Conditions Dimensions Dimensions Orientation MountingIntegration Guidance C141-E144 PCA FrameLimitation of mounting Location of breather Ambient temperature Handling cautions Service area Handling cautions Cable Connections Device connector Cable connector specifications Cable connector specificationsDevice connection FCI Location of setting jumpers Jumper SettingsPower supply connector CN1 Master drive-slave drive setting Factory default setting 14 Csel setting Csel setting 16 Example 2 of cable select Power up in standby setting Theory of Device Operation Subassemblies OutlineDisk Spindle Air filter Circuit ConfigurationServo circuit Spindle motor driver circuit Power supply configuration PCA Power-on operation sequence Power-on Sequence Self-calibration Self-calibration contents Execution timing of self-calibration Command processing during self-calibration Read/write preamplifier PreAMP Read/write CircuitWrite circuit Write precompensation Programmable filter circuit Read circuitAGC circuit FIR circuit Digital PLL circuitD converter circuit Viterbi detection circuit Servo control circuit Servo Control Microprocessor unit MPU Power amplifierServo burst capture circuit A converter DAC VCM current sense resistor CSR Driver circuit Inner guard band Data-surface servo formatData area Outer guard band Physical sector servo configuration on disk surface Servo frame format Operation to move the head to the reference cylinder Actuator motor controlSeek operation Track following operation Acceleration mode Start modeStable rotation mode Spindle motor control This page is intentionally left blank Interface Physical Interface Interface signals Signal assignment on the interface connector Signal assignment on the connectorDA1 PDIAG-, Cblid DA0 DA2 Dasp GND Diow MstrStop Dior Cblid PdiagDasp Iordy Logical Interface DA2 DA1 DA0 1 I/O registersI/O registers Error register X’1F1’ Command block registersData register X’1F0’ UNC Idnf Sector Count register X’1F2’ Features register X’1F1’SET Multiple Mode Cylinder High register X’1F5’ Sector Number register X’1F3’Cylinder Low register X’1F4’ DEV HS3 HS2 HS1 HS0 Device/Head register X’1F6’Status register X’1F7’ BSY Interface Alternate Status register X’3F6’ Command register X’1F7’Control block registers Command code and parameters Host CommandsDevice Control register X’3F6’ HOB Srst Parameter Used Command code and parameters 1 EXT Write Multiple FUA EXT Flush Cache EXT Command code and parameters 2 Host Commands Command descriptions Host Commands Recalibrate X’10’ to X’1F’ MSB Read Sectors X’20’ or X’21’ End head No. / LBA MSB Write Sectors X’30’ or X’31’ 1F7HST Status information 1F6HDH Write Verify X’3C’ Read Verify Sectors X’40’ or X’41’ Seek X’70’ to X’7F’ Diagnostic code Execute Device Diagnostic X’90’ Host Commands Initialize Device Parameters X’91’ Download Microcode X’92’ Operation of Download Microcode Standby Immediate X’94’ or X’E0’ Unload Feature Unload Immediate Command Host Commands Standby X’96’ or X’E2’ Idle X’97’ or X’E3’ Interface ’FF’ Check Power Mode X’98’ or X’E5’ Sleep X’99’ or X’E6’ Smart X’B0 Features register values subcommands and functions 1 Smart Enable Operations Features register values subcommands and functions 2Smart Disable Operations Smart Read LOG Smart Return Status Features register values subcommands and functions 3’DB’ Smart ENABLE/DISABLE Auto OFF-LINE Host Commands Format of insurance failure threshold value data Format of device attribute value data1FF Attribute ID Data format version number Current attribute value Status FlagAttribute value for the worst case so far Raw attribute value 11 Self-test execution status 10 Off-line data collection statusSelf-test execution status 12 Off-line data collection capability Off-line data collection capabilityFailure prediction capability flag 13 Failure prediction capability flag 14 Error logging capability Error logging capabilityCheck sum Insurance failure threshold Smart error logging 16 Data format of Smart Summary Error Log Error data structure Command data structureTotal number of drive errors 17 Data format of Smart Comprehensive Error Log 18 Smart self-test log data format Smart self-test1FC Self-test number Test span 19 Selective self-test log data structureCurrent LBA under test Current span under test Selective self-test pending time min Feature flags20 Selective self-test feature flags Device Configuration Restore Device Configuration XB1Device Configuration Freeze Device Configuration Identify Device Configuration Freeze Lock FR = C1h Device Configuration Restore FR = C0hDevice Configuration Identify FR = C2h Device Configuration SET FR = C3h Interface 21 Device Configuration Identify data structure Interface Read Multiple X’C4’ Execution example of Read Multiple command MSB Write Multiple X’C5’ Interface SET Multiple Mode X’C6’ Interface Read DMA X’C8’ or X’C9’ End head No. / LBA MSB Write DMA X’CA’ or X’CB’ Interface Read Buffer X’E4’ Flush Cache X’E7’ Write Buffer X’E8’ Identify Device X’EC’ Identify Device DMA X’EE’ ’3FFF’ 22 Information to be read by Identify Device command 1 22 Information to be read by Identify Device command 2 Word Command without interrupt supports 2, 4, 8 and 16 sectors = Supports the Host Protected Area feature set = Supports the CFA Compact Flash Association feature set Interface Host Commands Interface Host Commands Word Bit Reserved Security level High, 1 Maximum 23 Features register values and settable modes SET Features X’EF’’BB’ ’CC’ Data Transfer Mode Advanced Power Management APM Automatic Acoustic Management AAM 24 Contents of Security SET Password data At command issuance I-O register contents 1F7hCM Security UNLOCKX’F2’ When the master password is selectedWhen the user password is selected Interface Security Erase Prepare X’F3’ Security Erase Unit X’F4’ Security Freeze Lock X’F5’ At command issuance I-O register contents 1F7hCM 26 Contents of security password Interface Read Native MAX Address X’F8’ SET MAX Address SET MAX X’F9’ SET MAX SET Password FR = 01h SET MAX Lock FR = 02h SET MAX Unlock FR = 03h SET MAX Freeze Lock FR = 04h Host Commands Read Sectors EXT X’24’ Option customizing Description Read DMA EXT X’25’ Option customizing Description Error reporting conditions Read Multiple EXT X’29’ Option customizing Description Read LOG EXT X2F Optional command Customize Description Host Commands Write Sectors EXT X’34’ Option customizing Description Write DMA EXT X’35’ Option customizing Description SET MAX Address EXT X’37’ Option customizing Description SET MAX LBA Write Multiple EXT X’39’ Option customizing Description Write DMA FUA EXT X’3D’ Option customizing Description Write LOG EXT X’3F’ Optional command Customize Description Host Commands Read Verify Sectors EXT X’42 Option customizing Description Write Multiple FUA EXT X’CE’ Option customizing Description Flush Cache EXT X’EA’ Option customizing Description 27 Command code and parameters 1 Error posting 27 Command code and parameters 2 Execute Device Diagnostic Initialize Device Parameters Command ProtocolPIO Data transferring commands from device to host Read Sectors Command protocol Protocol for command abort PIO Data transferring commands from host to device Write Sectors command protocol Commands without data transfer DMA data transfer commands Other commandsRead Multiple EXT Write Multiple EXT/FUA EXT Sleep Read DMA EXT Write DMA EXT/FUA EXT Indentify Device DMA Normal DMA data transfer Overview Ultra DMA Feature Set Initiating an Ultra DMA data in burst Phases of operationUltra DMA data in commands Data in transfer Pausing an Ultra DMA data in burst Terminating an Ultra DMA data in burst Ultra DMA Feature Set Interface Initiating an Ultra DMA data out burst Ultra DMA data out commands Data out transfer Pausing an Ultra DMA data out burst Terminating an Ultra DMA data out burst Interface Ultra DMA CRC rules 28 Recommended series termination for Ultra DMA Series termination required for Ultra DMADIOR-HDMARDY-HSTROBE DIOW-STOP PIO data transfer timing TimingPIO data transfer Multiword data transfer 10 Multiword DMA data transfer timing mode 11 Initiating an Ultra DMA data in burst Ultra DMA data transfer Strobe Name Mode Comment MIN MAX 29 Ultra DMA data burst timing requirements 2 30 Ultra DMA sender and recipient timing requirements Mode Name Comment Dstrobe at device Sustained Ultra DMA data in burstDD150 at device Dstrobe at host DD150 at host Dmarq Host pausing an Ultra DMA data in burstDmack Hdmardy Stop Device terminating an Ultra DMA data in burst DA0, DA1, DA2 CS0, CS1 Host terminating an Ultra DMA data in burstHost 16 Initiating an Ultra DMA data out burst Hstrobe at device DD150 at device Sustained Ultra DMA data out burstHstrobe at host DD150 at host Hstrobe host DD150 Host Device pausing an Ultra DMA data out burstDevice DMACK- host Stop host DDMARDY- device 19 Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst DD150 Host Device terminating an Ultra DMA data out burstDmarq device DMACK- host Only master device is present Power-on and resetMaster and slave devices are present 2-drives configuration Operations Response to power-on Device Response to the Reset Response to power-on Response to hardware reset Response to hardware reset Response to software reset Response to software reset Response to diagnostic command Response to diagnostic command Power save mode Power SaveActive mode Active idle mode Sleep mode Standby mode Spare area Power commandsDefect Processing Track slip processing Alternating processing for defective sectorsSector slip processing Automatic alternating processing Automatic alternating processing 8MB buffer 8,388,608 bytes Read-ahead CacheData buffer structure Caching operation Commands that are targets of cachingData that is a target of caching Invalidating caching-target data Smart Miss-hit Using the read segment buffer Sequential hit Full hit Partial hit Write Cache Command that are targets of cachingCache operation Invalidation of cached data Reset response Status report in the event of an errorCaching function when power supply is turned on Enabling and disabling Write Cache This page is intentionally left blank Glossary Rotational delay Power save modePIO Programmed input-output Positioning VCM Status This page is intentionally left blank Acronyms and Abbreviations This page is intentionally left blank AAM Index Index Host terminating ultra DMA data Read Native MAX Address Read Sectors Command Surface temperature measurement This page is intentionally left blank Japan Comment Form This page is intentionally left blank C141-E218-01EN MHV2120AT, MHV2100AT, MHV2080AT, MHV2060AT, MHV2040AT This page is intentionally left blank