IFB Usage Considerations

Table 10-14. IFB Settings Checklist

Register

Type

Offset

Value

Comments

 

 

 

 

 

PCI Command Register

PCI

04h

0005h

Ensure that bits 0 and 2 are ‘1’

 

 

 

 

 

PCI Master Latency Timer

PCI

0Dh

 

 

 

 

 

 

 

PCI Bus Master IDE Base I/O Address

PCI

20-23h

 

Ensure that bit 0 (of register value) is ‘1’

 

 

 

 

 

IDE Timing Register 1

PCI

40-41h

 

 

 

 

 

 

 

IDE Timing Register 2

PCI

42-43h

 

 

 

 

 

 

 

Secondary IDE Timing Register

PCI

44h

 

 

 

 

 

 

 

Ultra DMA Control Register

PCI

48h

 

 

 

 

 

 

 

Ultra DMA Timing Register

PCI

4A-4Bh

 

 

 

 

 

 

 

10.5.9Example Configurations

This section provides examples of drive configurations on a IFB-based system.

10.5.9.1Example #1: Ultra DMA/33 Configuration

 

 

 

Best

 

 

 

 

Non Ultra DMA

Fast PIO

 

 

 

 

 

IFB Ultra

 

Supported?

 

 

 

Ultra

Best DMA

Best PIO

IFB

Supported?

Drive

Type

Position

DMA

Best DMA

DMA

Mode

Mode

Mode

Best PIO Mode >=

 

 

 

Mode

Mode is {SW2,

 

 

 

Mode

 

 

 

Best DMA Mode

 

 

 

 

 

 

 

MW1, MW2}

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Drive 0

Fixed Disk

Primary

Ultra

Multi Word

PIO4

Ultra

Mode 4

yes

yes

 

 

Single

DMA

DMA Mode

 

DMA

 

 

 

 

 

 

Mode 2

2

 

Mode 2

 

 

 

 

 

 

 

 

 

 

 

 

 

Drive 2

ATAPI

Secondary

Ultra

Multi Word

PIO3

Ultra

Mode 3

yes

yes

 

CDROM

Single

DMA

DMA Mode

 

DMA

 

 

 

 

 

 

Mode 1

1

 

Mode 1

 

 

 

 

 

 

 

 

 

 

 

 

 

In the above configuration, since both drives support Ultra DMA, Ultra DMA will be enabled on each of the drives: Ultra DMA Mode 2 for Drive 0 and Ultra DMA Mode 1 for Drive 1. Non-ultra DMA and Fast PIO support will be enabled on each drive as well.

Register

Type

Offset

Value

Comments

 

 

 

 

 

PCI Command Register

PCI

04h

0005h

Ensure that bits 0 and 2 are ‘1’.

 

 

 

 

 

PCI Master Latency Timer

PCI

0Dh

system dependent

 

 

 

 

 

 

PCI Bus Master IDE Base I/O

PCI

20-23h

system dependent

Ensure that bit 0

Address

 

 

 

(of register value) is ‘1’.

 

 

 

 

 

IDE Timing Register 1

PCI

40-41h

A307h

mode config. for Primary

 

 

 

 

 

IDE Timing Register 2

PCI

42-43h

A303h

mode config. for Secondary

 

 

 

 

 

Secondary IDE Timing Register

PCI

44h

00h

 

 

 

 

 

 

Ultra DMA Control Register

PCI

48h

05h

Drive 0 and 2 are Ultra DMA

 

 

 

 

capable.

 

 

 

 

 

Ultra DMA Timing Register

PCI

4A-4Bh

0102h

Ultra DMA mode config.

 

 

 

 

 

10-14

Intel® 460GX Chipset Software Developer’s Manual