Register Descriptions

2.4.6WXB2.4.6.1ERRSTS: Error Status Register

Address Offset:

44h

Size:

8 bits

Default Value:

00h

Attribute:

Read/Write Clear,

Sticky

 

 

 

This register records certain error conditions detected from the PCI bus. This register is sticky through reset; that is, the contents of the register remain unchanged during and following the assertion of XRST#. This allows system recovery software invoked following a forced reset to examine the flags to determine the cause of an error. Once set, the flags remain set until explicitly cleared by software or a power-goodreset.

Note: Bits 6, 4, and 2 are Reserved on side-b and records a zero value only!

Bits Description

7INTRQ Asserted Flag

This flag is set if the WXB has initiated an INTRQ interrupt event. This bit remains set, and the event signaled, until explicitly cleared by software writing a 1 to this bit. Default = 0.

6XBINIT Asserted Flag

This flag is set if the WXB has asserted XBINIT#. This bit remains set, and the event signaled, until explicitly cleared by software writing a 1 to this bit. Default = 0.

Note: This bit is Reserved on side-b and records a zero value only!

5NEPCI Register Records an PCI Bus Error Flag

This flag is set when the PCI bus reports an error (e.g. data parity error) on transactions to/from other PCI bus agents. This bit remains set until explicitly cleared by software writing a 1 to this bit. This bit is only set when the error is reported through the NEPCI Next Error register, indicating that the error is not the first error occurrence since the First Error register was last cleared. Default = 0.

4reserved (0)

3FEPCI Register Records an PCI Bus Error Flag

This flag is set when the PCI bus reports an error (e.g. data parity error) on transactions to/from other PCI bus agents. This bit remains set until explicitly cleared by software writing a 1 to this bit. This bit is only set when the error is reported through the FEPCI register, indicating that the error is the first error occurrence since the FEPCI register was last cleared. Default = 0.

2reserved (0)

1Performance Monitor #1 Event Flag

This flag is set when the Performance Monitor #1 detects an event. The

PCI_WXB_PMC1 registers describes the conditions that can cause this to occur. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default = 0.

0Performance Monitor #0 Event Flag

This flag is set when the Performance Monitor #0 detects an event. The

PCI_WXB_PMC0 registers describes the conditions that can cause this to occur. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default = 0.

Intel® 460GX Chipset Software Developer’s Manual

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