IDE Configuration

Table 12-4. Interrupt/Activity Status Combinations

Bit 2

Bit 0

Description

 

 

 

0

1

DMA transfer is in progress. No interrupt has been generated by the IDE device.

 

 

 

1

0

The IDE device generated an interrupt and the Physical Region Descriptors

 

 

exhausted. This is normal completion where the size of the physical memory regions

 

 

is equal to the IDE device transfer size.

 

 

 

1

1

The IDE device generated an interrupt. The controller has not reached the end of

 

 

the physical memory regions. This is a valid completion case when the size of the

 

 

physical memory regions is larger than the IDE device transfer size.

 

 

 

0

0

Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data to/

 

 

from memory. Specifics of the error have to be determined using bus-specific

 

 

information. If the Error bit is 0, the PRD specified a smaller buffer size than the

 

 

programmed IDE transfer size.

 

 

 

12.3.3BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O)

Address Offset:

Primary Channel–Base + 04h; Secondary Channel–Base + 0Ch

Default Value:

00000000h

Attribute:

Read/Write

This register provides the base memory address of the Descriptor Table. The Descriptor Table must be DWord aligned and not cross a 4 KByte boundary in memory.

Bit

Description

31:2 Descriptor Table Base Address (DTBA). Bits [31:2] correspond to A[31:2].

1:0 Reserved.

Intel® 460GX Chipset Software Developer’s Manual

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