Interrupt/Activity Status Combinations, 312 | Intel 460GX specs

IDE Configuration

Table 12-4. Interrupt/Activity Status Combinations

Bit 2	Bit 0	Description

0	1	DMA transfer is in progress. No interrupt has been generated by the IDE device.

1	0	The IDE device generated an interrupt and the Physical Region Descriptors
		exhausted. This is normal completion where the size of the physical memory regions
		is equal to the IDE device transfer size.

1	1	The IDE device generated an interrupt. The controller has not reached the end of
		the physical memory regions. This is a valid completion case when the size of the
		physical memory regions is larger than the IDE device transfer size.

0	0	Error condition. If the IDE DMA Error bit is 1, there is a problem transferring data to/
		from memory. Specifics of the error have to be determined using bus-specific
		information. If the Error bit is 0, the PRD specified a smaller buffer size than the
		programmed IDE transfer size.

12.3.3BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O)

Address Offset:	Primary Channel–Base + 04h; Secondary Channel–Base + 0Ch
Default Value:	00000000h
Attribute:	Read/Write

This register provides the base memory address of the Descriptor Table. The Descriptor Table must be DWord aligned and not cross a 4 KByte boundary in memory.

Bit	Description

31:2	Descriptor Table Base Address (DTBA). Bits [31:2] correspond to A[31:2].

1:0	Reserved.

Intel® 460GX Chipset Software Developer’s Manual

12-11

Image 243

Intel 460GX manual Interrupt/Activity Status Combinations, Is equal to the IDE device transfer size, 312

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 System Overview Introduction Component Overview Intel 460GX Chipset ComponentsName Function Itanium Processor System Bus Support Product Features PXB Features Dram Interface SupportI/O Support GXB Features RAS Features Programmable Interrupt Device PID Other Platform ComponentsReference Documents 1 I/O & Firmware Bridge IFB Date Description June Initial release Revision History Introduction Register Descriptions Access Mechanism Device Access RestrictionsPartitioning Device Mapping on Bus CBN Reserved or Undefined Register Locations Default Upon ResetRegister Attributes Reserved Bits Defined in Registers Gart Programming Region Configaddress Configuration Address RegisterI/O Mapped Registers Consistency 1.1 Error Handling RegistersConfigdata Configuration Data Register 1 SAC Valid Bits Description Disable1.2 1.3 Ferrsac First Error Status Register Nerrsac All Error Status Register Biuitid BIU Itid Register Saferr System Address on First Error Address bits Biudata BIU Data Register 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2 SDC2.1 SEC0DFERR Data on First Memory Card B SEC 2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2.7 SEC1DFERR Data on First Memory Card a SEC 2.4 DED0DFERR Data on First Memory Card B DED2.5 DED0ECCFERR ECC on First Memory Card B DED 2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.8 SEC1ECCFERR ECC on First Memory Card a SEC 2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC2.10 DED1DFERR Data on First Memory Card a DED Sdcferr First Error Status Register 2.11 DED1ECCFERR ECC on First Memory Card a DED2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED 14 ’Forward’ Underflow Card B Left Stack Error FL0 22 ’Forward’ Underflow Card a Right Stack Error FR121 ’Forward’ Underflow Card a Left Stack Error FL1 15 ’Forward’ Underflow Card B Right Stack Error FR0 Sdcnerr SDC Next Error Status Register Pcmdferr Command on First Pcmd Parity ErrorPitidferr Data on First Pitid Parity Error Sdcrspferr Response on First Sdcrsp Error Dpbrleferr Private Data Bus Receive Length ErrorECCMSK0 ECC Mask Register Card B ParMskP PB Parity Mask and IB Correction Enable Register ECCMSK1 ECC Mask Register Card aEccmskf ECC Mask Register Pvddferr Data on First PVD Parity Error Pvdparferr Parity on First PVD Parity ErrorPvdtxinfoferr Txinfo on First PVD Parity Error Dedfdferr Data on First System Bus DED Secfdferr Data on First System Bus SECSecfeccferr ECC on First System Bus SEC Secftxinfoferr Txinfo on First System Bus SEC Dedfeccferr ECC on First System Bus DED Ferrmac First Error Status RegisterQue-Overflow Error 3 MAC Cmndferr Command on First Error Errsts Error Status Register4 PXB Errcmd Error Command Register Ferrpci Ferragp First Error Status Register for AGP5 GXB 5.1 Nerragp Next Errors Status Register for AGP Ferrgart First Error Status Register for Gart Pacerr PCI Address & Cmd First Error Pderr PCI Data First ErrorNerrgart Bits Description Intrq Asserted Flag Nepci Register Records an PCI Bus Error FlagFepci Register Records an PCI Bus Error Flag 6 WXB Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register 6764 C/BE30 6332 AD6332 310 AD310 Fepcial PCI First Error Address/Command LogFepcidl PCI First Error Data Log Performance Monitor Registers Dmask Encodings OverflowCount Value Length Encodings Event Select Umask Encodings Disable Source Enable SourceReload Control 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3 PXB 3.1 PMD10 Performance Monitoring Data Register3.2 PMR10 Performance Monitoring Response Initiating Agent Selection Reload Mode3.3 PME10 Performance Monitoring Event Selection Count Data Cycles AGPPMD0,1 AGP Performance Monitor Data Registers 4 GXB Pcipmd PCI Performance Monitor Data Registers Percon Performance Monitor Control RegisterEvent 1 Input AGPPMC0,1 AGP Performance Monitor Configuration Register Event 0 InputPipe or Sideband Request Mask Pcipmc PCI Performance Monitor Configuration Register EVENT1 Count EnableInitiating Agent Disable Source Issuing Agent Qualifier PCIWXBPMC0 PCI Performance Monitor Configuration Register5 WXB Data Transfer and Transaction Qualifier PCIWXBPMC1 PCI Performance Monitor Configuration Register Interrupt Related RegistersXtprs External Task Priority Registers Memory-Mapped Register Summary Address Name Access Default ValuePID PCI Memory-mapped Registers 2.1 I/O Register Select Register FEC00000h I/O Window Register Format PID Indirect Access Registers2.2 I/O Window Register FEC00010h XAPIC EOI Register FEC00040h Offset Name Access Default Value 3.1 I/O xAPIC ID Register 00hRTE Memory-mapped Register Summary Cont’d I/O xAPIC Version Register Format 3.2 I/O xAPIC Version Register 01h3.3 I/O xAPIC Arbitration ID Register 02h I/O Apic ID Register Format 10. I/O xAPIC RTE Format Bits Sapic Mode Apic Mode Description Name3.4 I/O xAPIC RTE 10h-8Fh I/O xAPIC Arbitration ID Register Format 10. I/O xAPIC RTE Format Cont’d Sapic Mode Apic Mode Description Name Vector Destination System Architecture CoherencyProcessor Coherency Ordering PCI CoherencyAGP Coherency WXB Arbitration WXB Arbitration at the PCI BusArbitration for Inbound Transactions Arbitration for Outbound Transactions Big-endian SupportIndivisible Operations Processor Locks Locks with AGP Non-coherent Traffic Inbound PCI LocksAtomic Writes Atomic Reads WXB PCI Hot-Plug Support Interrupt Delivery Slot Power-down and Disable Slot Power-up and Enable System Architecture System Address Map Memory MapCompatibility Region System Memory Address Space System Firmware Medium Extended Memory Region Low Extended Memory Region High Extended Memory above 4G Re-mapped Memory AreasVariable GAP Itanium Processor and Chipset-specific Memory Space I/O Address Map System I/O Address Space High PXB must ignore GXB must BINIT# after Gart Devices View of the System Memory Map Legal and Illegal Address Disposition Address DispositionAddress Range Outbound Inbound Dest. Decision Binit Address Disposition Cont’dMain memory if present above 4 GB Above TOM System Address Map System General Memory CharacteristicsMemory Subsystem Organization Maximum Memory Configuration Using Two Cards Double Number Memory Size Minimum/Maximum Memory Size per ConfigurationTechnology & Configuration Size Dimm Types Address Interleaving Interleaving/Configurations Summary of Configuration Rules Non-uniform Memory ConfigurationsBandwidth Removing a Bad Row Supporting FeaturesMemory Subsystem Clocking Auto Detection Memory Size Time to Scrub Hardware InitializationMemory Scrubbing Scrubbing Time Memory Subsystem Data Integrity and Error Handling IntegritySystem Bus 5 AGP DramExpander Buses PCI Buses Usage of First-error and Next-error Memory ECC RoutingData Poisoning Masked Bits BERR#/BINIT# GenerationINTREQ# XSERR# SAC/SDC ErrorsData ECC or Parity Errors XBINIT# SAC to SDC Interface Errors System Bus Errors 5 SDC/Memory Card Interface Errors SAC to MAC Interface Errors Error Determination 6 SDC/System Bus ErrorsSDC Internal Errors SAC Address on an Error Special Notes on Usage of SECTID, DEDTID, Fsetid Registers SDC Logging Registers Clearing Errors Multiple Errors1 SAC/SDC Error Clearing ERR ERR SDC Multiple Errors SAC Multiple Errors Single Errors with Multiple ReportingError Anomalies SAC Error Flow on Data Data Flow Errors Table of Errors Error Conditions Error Cases SAC to SDC Interface ErrorsSystem Bus ADD/CMND Error Cases Cont’d Internal SDC Error Detected as PCI Master PXB Errors Master Abort PCI IntegrityPCI Bus Monitoring PXB as Master PXB as Target GXB Error Flow Target RetryTarget Abort GXB Errors GXB Error Signals Gart Interface Errors GXB Error Flow Multiple Errors Data Parity Poisoning WXB Data Integrity and Error HandlingUsage of First Error and Next Error Registers Integrity Abbreviation Error Error Mask BitsError Steering/Signaling Supported Error Escalation to XBINIT#a Escalation Supported Error Escalation to SERROUT#aSupported Error Escalation to PA/BINTRQ# SERR# Generation Error Determination and Logging INTRQ# InterruptXBINIT# Generation WXB as Bus Master Error Conditions Other Violations WXB as Target PCI Interface Errors System Error SignaledDiscard Timer Expiration Graphics Address Relocation Table Gart AGP Subsystem 14b 12b24b 22b Gart Entry Format for 4kB Pages Gart Implementation Parity Programming GartSizes Gtlb Coherency SGW#SE2 ADSC# ADSP# ADV# LBO# SB# SW# Addresses Used by the Graphics Card 4.1 3.3V AGP 1X and 2X Mode CompatibilityAGP Traffic Interrupt Handling Coherency, Translation and Types of AGP Traffic Traffic Priority Ordering Rules Processor Locks and AGP TrafficCoherency for AGP/PCI Streams Inbound Reads Address FaultsAddress Alignment and Transfer Sizes PCI Semantics Traffic Inbound Delayed Read Matching Rules PCI Stream Read PrefetchingInbound Reads Directed To Memory Inbound Writes Delayed Read Matching CriteriaCommand Address BEs Inbound I/O Reads Retry/Disconnect Conditions Outbound ReadsOutbound Writes 1st write 2nd write 3rd write Transferred as Transfer Data Length Combining Supported Used ModeFast Back-to-Back Transactions Burst Write Combining Modes Bandwidth Estimates for Various Request Sizes LatencyGXB Address Map Inbound Read Prefetching AGP Subsystem AGP Subsystem WXB Hot-Plug Ihpc Configuration Registers Ihpc Configuration Register Space Number List for the Ihpc PCI Register Descriptions VID Vendor Identification RegisterDid Device Identification Register Pcicmd PCI Command Register RID Revision Identification Register Pcists PCI Status Register HDR Header Register MLT Master Latency Timer RegisterClass Class Register CLS Cache Line Size Interrupt Line Base AddressSvid Subsystem Vendor Identification SID Subsystem ID Miscellaneous Hot-Plug Configuration Interrupt PinHot-Plug Slot Identifier Hot-Plug Features Switch Change Serr StatusPower Fault Serr Status Arbiter Serr Status Memory Access IndexMemory Mapped Register Access Port Ihpc Memory Mapped Registers M66EN Ihpc Memor Mapped Register Space Number List for Ihpc Memory Mapped Register Descriptions Slot Enable LED Control Hot-Plug Miscellaneous Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data Serial Input Byte Pointer General Purpose OutputHot-Plug Non-interrupt Inputs Hot-Plug Switch Interrupt Redirect Enable Slot Power ControlExtended Hot-Plug Miscellaneous IFB Register Mapping PCI / LPC / FWH ConfigurationPCI Configuration Registers Function Mnemonic Register Register Access Hedt BiosenPcists Classc PCI Configuration Registers-Function 1 IDE Interface IDE Configuration Universal Serial Bus USB Configuration PCI Configuration Registers-Function 2 USB InterfaceConfiguration Offset Mnemonic Register SMBus Configuration Registers Function SMBus Controller Configuration IFB Register Mapping IFB Usage Considerations Usage of 1MIN Timer in Power ManagementUsage of the SW SMI# Timer CD-ROM Auto RUN Feature of the OS SSDE1 SSDE0 PSDE1 PSDE0 Ultra DMA ConfigurationReserved Secondary Primary Drive Ultra DMA Mode Enable Disabled Enabled Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities Determining a Drive’s Transfer Rate CapabilitiesOverview Capability Word Bits Field Offset Capability Word Bits DMAPIO Capability Word Bits Field Determining a Drive’s Best Ultra DMA Capability Capability Word Offset Bits Field 150 Minimum Multi Word DMA Transfer Cycle Time per10-6 Determining a Drive’s Best PIO Capability Drives Reported DMA Drive’s Best DMA Mode Cycle Time Drive PIO Capability as a Function of Cycle Time Drives Reported PIO Drive’s Best PIO Mode Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk IFB Timing Settings10.5.6.1 DMA/PIO Timing Settings IFB Drive Mode Based on DMA/PIO Capabilities DMA Iordy IDE DMA/PIO Timing Values Based on Piix Cable Mode/System Speed Drive Configuration for Selected TimingsUltra DMA Timing Settings 10. Ultra DMA Timing Value Based on Drive Mode 12. PIO Transfer/Mode Values Drive’s Selected PIO Speed Capability10-12 13. Drive Capabilities Checklist Settings Checklist Register Type Offset Value Comments Example ConfigurationsExample #1 Ultra DMA/33 Configuration 14. IFB Settings Checklist 44h 0Bh Ultra DMA Control Register Example #3 Non Ultra DMA/33 Drive Configuration40-41h E377h Mode config. for Primary IDE Timing Register 4A-4Bh 0002h Ultra DMA mode config Ultra DMA System Software Considerations 4A-4Bh 0000h10-16 Intel 460GX Chipset Software Developer’s Manual 10-17 Completed or halted Bit Description Reserved. This bit is hardwired toBMISX-Bus Master IDE Status Register I/O Bit Description Bit Type Description USB Resume Enable Bit 10-20 LPC/FWH Interface Configuration VID-Vendor Identification Register FunctionDID-Device Identification Register Function PCISTS-PCI Device Status Register Function PCICMD-PCI Command Register Function Bit RID-Revision Identification Register FunctionCLASSC-Class Code Register Function HEDT-Header Type Register Function Acpi Enable Function Acpi Base Address FunctionSCI IRQ Routing Control PIRQRCAD-PIRQx Route Control Registers Function BIOSEN-BIOS Enable Register Function TOM-Top of Memory Register Function SerIRQC-Serial IRQ Control Register Function Deterministic Latency Control Register Function MSTAT-Miscellaneous Status Register Function PDMACFG-PCI DMA Configuration Resister Function O MGPIOC-Muxed Gpio Control FunctionBits Description Base Offset Channel RTCCFG-Real Time Clock Configuration Register Function Bits Decode Range Gpio Enable FunctionGpio Base Address Function LPC COM Decode Ranges Function 110 LPC FDD/LPT Decode Ranges Function000 011 11-12 LPC Sound Decode Ranges FunctionLPC Generic Decode Range Function 220 233 240 253 260 273 280 293 1413 Reserved LPC Enables FunctionFirmware Hub FWH Decode Enable Register Reserved. This bit must be a Firmware Hub FWH Select Register DMA Registers Test Mode RegisterDcom-Dma Command Register I/O PCI to LPC I/O Space Registers Dr-Dma Request Register I/O Dcm-Dma Channel Mode Register I/O WSMB-Write Single Mask Bit I/O RWAMB-Read / Write All Mask Bits I/OBit Description Reserved. Must be DBADDR-DMA Base and Current Address Registers I/O Ds-Dma Status Register I/O DCBP-Dma Clear Byte Pointer Register I/O When counting down a DMA transferDBCNT-Dma Base and Current Count Registers I/O DLPAGE-DMA Low Page Registers I/O Dclm-Dma Clear Mask Register I/O 11.2.2.1 Icw1-Initialization Command Word 1 Register I/OInterrupt Controller Registers Dmc-Dma Master Clear Register I/O 11.2.2.2 Icw2-Initialization Command Word 2 Register I/O 11.2.2.3 Icw3-Initialization Command Word 3 Register I/OBit Description Reserved. Must be programmed to all 0s 11-22 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O11.2.2.5 Icw4-Initialization Command Word 4 Register I/O 11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O Elcr1-Edge/Level Control Register I/O Bit Decription Counter/Timer RegistersTcw-Timer Control Word Register I/O Elcr2-Edge/Level Control Register I/O 5. When bit 1=0, status and/or count will not be latched Latched. When bit 4=1, the status will not be latched5. When bit 3=0, status and/or count will not be latched 5. When bit 2=0, status and/or count will not be latched TMRCNT-Timer Count Registers I/O TMRSTS-Timer Status Registers I/O Nmisc-Nmi Status and Control Register I/O NMI Registers Used for NMI enabling/disabling. See description in Section NMI Enable. Used by IFB NMI logicReal Time Clock Registers RTCD-Real-time Clock Data Register I/O RTCED-Real-time Clock Extended Data Register I/O Advanced Power Management APM RegistersAPMC-Advanced Power Management Control Port I/O RTCEI-Real-time Clock Extended Index Register I/O APMS-Advanced Power Management Status Port I/O Power Management 1 StatusAcpi Registers 11-32 Power Management 1 EnablePower Management 1 Control States can be supported in external logic 3124 Reserved 230 Power Management 1 TimerBit Description Bits Mode General Purpose 0 Status CF9 write General Purpose 0 EnablePower up, this bit is set to ‘1’ 1512 Reserved General Purpose 1 Enable SMI RegistersGeneral Purpose 1 Status Thrmsts bit Global Control and EnablePort at B2h in I/O space Status Register is set GPIO7 General Purpose I/O RegistersGlobal Status Register GPIO8 GP Data GP Output Bit is set GP TTL1916 159 Reserved GP Blink GP LockGP Invert GP Pull-up GP SMIGP Pulse GP Core 11-42 IDE Controller Register Descriptions PCI Function IDE ConfigurationPCI Configuration Registers Function Configuration Mnemonic Register VGA Palette Snoop. This bit is hardwired to SERR# Enable. This bit is hardwired toWait Cycle Control. This bit is hardwired to Parity Error Response. This bit is hardwired to By writing a 1 to this bit SERR# Status. Read as MLT-Master Latency Timer Register Function BMIBA-Bus Master Interface Base Address Register FunctionBus Master interface registers and correspond to AD154 SVID-Subsystem Vendor ID Function SID-Subsystem ID FunctionIDETIM-IDE Timing Register Function SIDETIM-Slave IDE Timing Register Function Bit Description Reserved DMACTL-Synchronous DMA Control Register Function SDMATIM-Synchronous DMA Timing Register Function Ultra DMA/33 Timing Modes BMICx-Bus Master IDE Command Register I/OUltra DMA/33 Timing Mode Settings IDE Controller I/O Space Registers BMISx-Bus Master IDE Status Register I/O Interrupt/Activity Status Combinations Is equal to the IDE device transfer size312 12-12 Universal Serial Bus USB Configuration PCI Configuration Registers-FunctionUsbren USB Host Controller Register Descriptions PCI Function Bit Description 1510 Reserved. ReadReserved. Read as Reserved. Read as 0’s Resets STA to 0 by writing a 1 to this bit This field Register in Function13-4 INTLN-Interrupt Line Register Function USBBA-USB I/O Space Base Address Function LEGSUP-Legacy Support Register Function INTPN-Interrupt Pin FunctionMiscellaneous Control Function SBRNUM-Serial Bus Release Number Function Accesses that are part of the sequence Default to 1 for compatibility with older USB softwareNeeds to be serviced later Appropriate enable bits are set USBREN-USB Resume Enable USBCMD-USB Command Register I/OUSB Host Controller I/O Space Registers By Software or Hardware Run/Stop, Debug Bit InteractionSwdbg Bit Run/Stop Bit Operation Stop=0, the Frnum register can be reprogrammed Register = USBINTR-USB Interrupt Enable Register I/OUSBSTS-USB Status Register I/O Interrupt is generated to the system SOFMOD-Start of Frame SOF Modify Register I/O Address signalsFRNUM-Frame Number Register I/O FLBASEADD-Frame List Base Address Register I/O PORTSC-Port Status and Control Register I/O Register define the hub states as follows X0 DisableAsserted, the corresponding port is disabled EOF2 time See of the USB Specification 13-14 Base Address Register SM Bus Controller ConfigurationSM Bus Configuration Registers Function Class Code 0C-1Fh Reserved System Management Register Descriptions Shutdown special cycle14-2 STA to 0 by writing a 1 to this bit 14-4 SMBBA-SMBus Base Address Function Interrupt pin PIRQB# is used Host Configuration Smbshdw2-SMBus Slave Shadow Port 2 Function Smbslvc-SMBus Slave Command FunctionSMBus I/O Space Registers Smbshdw1-SMBus Slave Shadow Port 1 Function Position Transaction errors are caused bySmbhststs-SMBus Host Status Register I/O Smbslvsts-SMBus Slave Status Register I/O Smbhstcnt-SMBus Host Control Register I/O Smbhstdat0-SMBus Host Data 0 Register I/O Smbhstcmd-SMBus Host Command Register I/OCommand field of SMBus host transaction Smbhstadd-SMBus Host Address Register I/O Smbhstdat1-SMBus Host Data 1 Register I/O Smbblkdat-SMBus Block Data Register I/OSmbslvcnt-SMBus Slave Control Register I/O Address 10h or one of the slave shadow port addresses 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/OSmbslvdat-SMBus Slave Data Register I/O 14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O 14-12 PCI/LPC Bridge Description PCI InterfaceInterrupt Controller Initialization Command Words ICWs Programming the Interrupt Controller15-2 End of Interrupt EOI Operation Command Words OCWsAutomatic End of Interrupt Aeoi Mode End of Interrupt Operation Automatic Rotation Equal Priority Devices Fully Nested ModeSpecial Fully Nested Mode Modes of Operation Cascade Mode Poll CommandSpecific Rotation Specific Priority Masking on an Individual Interrupt Request Basis Edge and Level Triggered ModeSpecial Mask Mode Interrupt Masks Interrupt Steering Reading the Interrupt Controller Status Protocol Quiet Active ModeContinuous Idle Mode Serial Interrupts 3222 Stop FrameSerirq Frames Data Frame Number Usage # Clocks Past Start Timer/Counters Programming the Interval Timer15-10 Write Operations Interval Timer Control Word Format 15-12 Counter Latch CommandRead Operations Counter I/O Port Read Real Time Clock Read Back Command RTC Registers and RAM RTC Standard RAM BankIndex Address Name 15.5.1.1 Register a 1 Invalid 0 Invalid90625 ms 8125 ms 15.5.1.2 Register B 15.5.1.3 Register CRSMRST# 15.5.1.4 Register D RTC Update CycleRTC Interrupts Lockable RAM Ranges 15-18 Acpi State Description IFB Power ManagementIFB Power States and Consumption Overview Causes of SMI# IFB Power PlanesPower Plane Descriptions 16.2.2 SMI# Generation SCI Event Comment SCI GenerationSleep States Causes of SCI# Offset Register Name/Function Comment Acpi Bits Not Implemented by IFBEntry/Exit for the S4 and S5 States Acpi Bits Not Implemented in IFB Handling of Power Failures in IFB Action after Power ReturnsS5 Wake Event Comment 16-6