Intel 460GX manual 4

3	System Architecture ........................................................................................................			3-1
	3.1	Coherency..........................................................................................................		3-1
		3.1.1	Processor Coherency............................................................................	3-1
		3.1.2	PCI Coherency......................................................................................	3-2
		3.1.3	AGP Coherency ....................................................................................	3-2
	3.2	Ordering .............................................................................................................		3-2
	3.3	Processor to PCI Traffic and PCI to PCI (Peer-to-Peer) Traffic .........................		3-3
	3.4	WXB Arbitration..................................................................................................		3-3
	3.5	Big-endian Support ............................................................................................		3-4
	3.6	Indivisible Operations.........................................................................................		3-4
		3.6.1	Processor Locks....................................................................................	3-4
		3.6.2	Inbound PCI Locks................................................................................	3-5
		3.6.3	Atomic Writes ........................................................................................	3-5
		3.6.4	Atomic Reads........................................................................................	3-5
		3.6.5 Locks with AGP Non-coherent Traffic ...................................................		3-5
	3.7	Interrupt Delivery................................................................................................		3-6
	3.8	WXB PCI Hot-Plug Support ...............................................................................		3-6
		3.8.1 Slot Power-up and Enable ....................................................................		3-7
		3.8.2 Slot Power-down and Disable ..............................................................		3-7
4	System Address Map ......................................................................................................			4-1
	4.1	Memory Map ......................................................................................................		4-1
		4.1.1	Compatibility Region .............................................................................	4-1
		4.1.2 Low Extended Memory Region .............................................................		4-3
		4.1.3 Medium Extended Memory Region.......................................................		4-3
		4.1.4 High Extended Memory (above 4G)......................................................		4-4
		4.1.5	Re-mapped Memory Areas ...................................................................	4-4
	4.2	I/O Address Map ................................................................................................		4-5
	4.3	Devices View of the System Memory Map.........................................................		4-7
	4.4	Legal and Illegal Address Disposition ................................................................		4-8
5	Memory Subsystem ........................................................................................................			5-1
	5.1	Organization.......................................................................................................		5-1
		5.1.1	DIMM Types..........................................................................................	5-3
	5.2	Interleaving/Configurations ................................................................................		5-4
		5.2.1 Summary of Configuration Rules ..........................................................		5-5
		5.2.2	Non-uniform Memory Configurations ....................................................	5-5
	5.3	Bandwidth ..........................................................................................................		5-5
	5.4	Memory Subsystem Clocking.............................................................................		5-6
	5.5	Supporting Features...........................................................................................		5-6
		5.5.1	Auto Detection.......................................................................................	5-6
		5.5.2 Removing a Bad Row ...........................................................................		5-6
		5.5.3	Hardware Initialization...........................................................................	5-7
		5.5.4	Memory Scrubbing ................................................................................	5-7
6	Data Integrity and Error Handling...................................................................................			6-1
	6.1	Integrity	..............................................................................................................	6-1
		6.1.1	System Bus ...........................................................................................	6-1
		6.1.2	DRAM....................................................................................................	6-2
		6.1.3	Expander Buses....................................................................................	6-2
		6.1.4	PCI Buses .............................................................................................	6-2
		6.1.5	AGP.......................................................................................................	6-2

iv Intel® 460GX Chipset System Software Developer’s Manual