LPC/FWH Interface Configuration

These registers provide the base address for distributed DMA slave channel registers, one for each DMA controller. Bits 5:0 are reserved to provide access to a 64 byte I/O space (16 bytes per channel). The channels are accessed using offset from base address as follows (Note that Channel 4 is reserved and is not accessible).

Base Offset

 

Channel

 

 

 

 

 

 

 

00

- 0Fh

 

0,4

 

 

 

 

 

 

 

 

10

- 1Fh

 

1,5

 

 

 

 

 

 

 

 

20

- 2Fh

 

2,6

 

 

 

 

 

 

 

 

30

- 3Fh

 

3,7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

 

 

 

Description

 

 

 

15:6

 

Base Pointer: I/O Address pointer to DMA Slave Channel registers. Corresponds to PCI

 

 

address AD[15:6].

 

 

 

 

 

5:0

 

Reserved.

 

 

 

 

 

 

 

 

11.1.20RTCCFG–Real Time Clock Configuration Register (Function 0)

Address Offset:

C8h

Default Value:

00h

Attribute:

Read/Write

This register is used to configure the internal Real Time Clock.

Bits

Description

 

 

7:5

Reserved.

 

 

4

Lock Upper RAM Bytes: 0 = Upper RAM data bytes 38h-3Fh in the extended bank are

 

readable and write-able (default). 1 = Upper RAM data bytes 38h-3Fh in the extended bank

 

are neither readable nor write-able. This is used to lock bytes 38h-3Fh in the upper 128-byte

 

bank of RAM. Write cycles will have no effect and read cycles will not return an expected

 

value.

 

Warning: This is a write-once register that can only be reset by a hardware reset. No

 

software means is possible to reset this bit.

 

 

3

Lock Lower RAM Bytes: 0 = Lower RAM data bytes 38h-3Fh in the standard bank are

 

readable and writeable (default). 1 = Lower RAM data bytes 38h-3Fh in the standard bank are

 

neither readable nor writeable. This is used to lock bytes 38h-3Fh in the lower 128-byte bank

 

of RAM. Write cycles will have no effect and read cycles will not return an expected value.

 

Warning: This is a write-once register that can only be reset by a hardware reset. No

 

software means is possible to reset this bit.

 

 

2

Upper RAM Enable: 0 = Accesses to RTC Upper 128 byte extended bank at I/O address 72-

 

73h is disabled. 1 = Accesses to 72-73h are forwarded to RTC Upper 128 byte extended

 

bank.

 

 

1:0

Reserved.

 

 

Intel® 460GX Chipset Software Developer’s Manual

11-9

Page 199
Image 199
Intel 460GX manual RTCCFG-Real Time Clock Configuration Register Function, Base Offset Channel