Intel 460GX System Address Map, 4.1Memory Map, 4.1.1Compatibility Region, 4.1.1.1DOS Region, 4.1.1.2VGA Memory, 4.1.1.3C, D, and E Segments

System Address Map 4

4.1Memory Map

The Itanium™ processor supports a 44 bit address space. The 460GX chipset supports only 36 bits of the address bus for a 64 GB of physical memory and must address up to several GB of memory mapped I/O space. The 460GX chipset attaches to A#[35:3].

The memory address space is divided into four regions: the 1 MB Compatibility Area, the 15 MB Low Extended Memory region, the (4 GB minus 16 MB) Medium Extended Memory region, and the (16 TB minus 4 GB) High Extended Memory region. The first three regions are divided into multiple subregions, with dedicated purpose and semantics. The memory address map is illustrated in Figure 4-1.

4.1.1Compatibility Region

This is the range from 0-1 MB (0_0000 to F_FFFF). Addresses here may be directed to a PCI bus (the compatibility bus) or main memory. Any DRAM located in this area that is not used as main memory is not recovered. This region is divided into four subregions, some of which are further subdivided. Regions below 1M that are mapped to memory are accessible by the processors and by any PCI bus.

Regions below 1M that are mapped to PCI are accessible by the processor, and by PCI devices on the targeted PCI bus (in the case of the regions mapped by the MAR this means the compatibility PCI bus; for the VGA region this means the PCI bus to which VGA is mapped). Parallel segment peer-to-peer accesses are not supported below 1M; a PXB will either forward the access to memory or let it be claimed/master abort on the PCI bus below it.

4.1.1.1DOS Region

The DOS Region is the lowest 640 KB, in the address range 0h to 9_FFFFh. DOS applications execute here. The lower 512K of this region is always mapped to main memory, and is accessible by the processors and by any PCI bus. The upper 128K of this region can be mapped to either PCI or main memory, and is mapped using one of the MAR registers. The range defaults to memory.

4.1.1.2VGA Memory

The 128 KB Video Graphics Adapter Memory subregion (A_0000h to B_FFFFh) is normally mapped to a video device on the compatibility PCI bus. Typically, this is a VGA controller. The 460GX chipset supports mapping this region to any of its logical PCI segments. At power-on this space is mapped to the compatibility PCI bus.

4.1.1.3C, D, and E Segments

The 192 KB C, D, and E Segments are divided into smaller blocks that can be independently programmed as Mapped to Memory, Memory Write Protect, In-line Shadowed, or Mapped to PCI. These regions are used to provide memory to PCI devices requiring memory space below 1 MB.

The MAR registers determine how each range is used. The default for these segments at power-on is that they are mapped read/write to the PCI compatibility bus.

Intel® 460GX Chipset Software Developer’s Manual 4-1