1.5.2 WXB Features
Supports the I/O and Firmware Bridge (IFB).
Supports two delayed inbound read requests.
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• Supports either internal or external arbitration, allowing additional bus masters, on the PCI bus.
— Combines back-to-back sequential processor-to-PCI memory writes to PCI burst writes.
— Processor to PCI write assembly of full/partial line writes.
• Two outbound read requests containing a total of two cache lines of read data for each PCI bus.
• Supports six outbound write requests containing a total of three cache lines of write data for each 32 bit PCI bus. Supports 12 outbound write requests containing a total of six cache lines of write data for a 64 bit PCI bus.
Parity protection on all PCI signals. Data collection & write assembly.
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Introduction

•Support for two 64 bit, 66 MHz PCI busses.

•3.3 Volt PCI bus operation (supports Universal and 3.3 Volt PCI cards).

•PCI Specification, Revision 2.2.

•Integrated Hot-Plug controller.

1.5.3GXB Features

•The GXB is AGP and AGP 4X mode compatible, nominal 66 MHz, 266 MHz, 1 GB/s peak bandwidth.

•The GXB supports pipelined operation or sideband signals on AGP 4X mode bus.

•AGP address space of 1 GB or 256 MB supported. Also supports 32 GB of GART window, if 4 MB pages are used.

•Supports Fast Writes and 1x, 2x and 4x data rates.

1.6RAS Features

• ECC coverage of system data bus using the Itanium™ processor SEC/DED ECC code. Memory is protected using a SEC/DED code which also provides nibble detection capabilities of 4 bits. All control and address signals are parity protected. Local control buses are parity protected. The Expander is covered by parity.

•Data flows protected by parity throughout chipset.

•ECC bits in DRAM accessible by diagnostics.

•Fault recording of multiple errors; sticky through reset, but NOT through power-down.

•Memory scrubbing implemented in hardware.

•Boundary test capability through JTAG.

•JTAG TAP port for debug.

Intel® 460GX Chipset Software Developer’s Manual

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