Intel 460GX manual Address Alignment and Transfer Sizes, PCI Semantics Traffic, Address Faults

AGP Subsystem

this point the inbound Expander logic establishes a pseudo-lock and will no-longer send coherent requests from the AGP streams. Non-coherent requests can still be issued, but anything that can block the PCI stream in the SAC’s queues must be held in the GXB.

5.The outbound Locked Write request is transferred across the Expander bus.

6.An Unlock transactions is transferred across the Expander bus (locked writes are posted; the Unlock will occur once the system bus lock goes away, so this will occur even if the data has not been delivered to its destination). The Unlock request, which throughout the Expander queues has the same semantics as a posted write, must be pushed into the outbound PCI queue behind the Locked Write.

7.When the Locked Write reaches the head of the outbound PCI queue it is performed on the AGP Bus with PCI semantics.

8.When the write completes on the AGP bus, a Write Completion is pushed into the inbound PCI transaction queue.

9.The Unlock transaction reaches the head of the outbound PCI queue.

10.A write completion for the Unlock transaction is placed in the inbound PCI transaction queue. At this point the PCI interface’s pseudo-lock is released.

11.Both the completion for the locked write and for the Unlock transaction are delivered over the Expander bus. When the Expander logic transmits the completion for the Unlock transaction, its pseudo-lock is released.

7.2.6Address Alignment and Transfer Sizes

The AGP specification allows the graphics card to request reads of size 8-64 bytes in eight-byte increments or of size 32 to 256 bytes in 32-byte increments. Reads and writes are both aligned on any 8-byte boundary. There is no concept of cache-line aligned or even page aligned. The request may cross a page boundary and require 2 translations. There is no requirement that the physical addresses resulting from the translation be contiguous. There is also no requirement that the coherency be the same on these two pages.

7.2.6.1Address Faults

See the ‘ERROR’ chapter for the GXB behavior on addresses that are considered illegal.

The graphics card may do AGP transfers to areas outside the GART range. There is no translation on these addresses, so the graphics card must use the physical DRAM address for the object it is attempting to access. This is perfectly acceptable, but the graphics card and device driver must be able to provide the correct physical address to be used.

7.2.7PCI Semantics Traffic

7.2.7.1Inbound Reads

Delayed Transactions

The GXB supports the Delayed Transaction mechanism as defined in the PCI 2.2 Specification. The process of latching all information required to complete the transaction, terminating with Retry, and completing the request without holding the master in wait-states is called a Delayed Transaction. The GXB will delay all memory space read requests (unless a delayed slot is unavailable); no other request types are delayed.

Intel® 460GX Chipset Software Developer’s Manual 7-9