Data Integrity and Error Handling

MWI to a misaligned (non-cache-line-boundary) address

MWI to an aligned address, but with one or more byte enables not asserted

Refer to the PCI specification for a complete description of the required PCI protocol.

6.12.8.3PCI Interface Errors

Other PCI interface errors that are handled by the WXB are:

System Error Signaled

Set within the FEPCI register when the WXB sees an SERR# asserted by another PCI agent. This is not set when the WXB drives SERR#.

Discard Timer Expiration

Set when the 215 timer expires. The timer starts approximately when the data for a delayed read is requested by the WXB. If the card doesn’t re-access the data in 215 PCI clocks, then an error is flagged.

6-32

Intel® 460GX Chipset Software Developer’s Manual