15

PCI/LPC Bridge Description..........................................................................................

15-1

 

15.1

PCI Interface ....................................................................................................

15-1

 

 

15.1.1

Transaction Termination .....................................................................

15-1

 

 

15.1.2

Parity Support .....................................................................................

15-1

 

 

15.1.3

PCI Arbitration.....................................................................................

15-1

 

15.2

Interrupt Controller ...........................................................................................

15-1

 

 

15.2.1 Programming the Interrupt Controller..................................................

15-2

 

 

15.2.2 End of Interrupt Operation...................................................................

15-3

 

 

15.2.3

Modes of Operation.............................................................................

15-4

 

 

15.2.4

Cascade Mode ....................................................................................

15-5

 

 

15.2.5 Edge and Level Triggered Mode.........................................................

15-6

 

 

15.2.6

Interrupt Masks ...................................................................................

15-6

 

 

15.2.7 Reading the Interrupt Controller Status...............................................

15-7

 

 

15.2.8

Interrupt Steering ................................................................................

15-7

 

15.3

Serial Interrupts................................................................................................

15-8

 

 

15.3.1

Protocol ...............................................................................................

15-8

 

15.4

Timer/Counters ..............................................................................................

15-10

 

 

15.4.1 Programming the Interval Timer........................................................

15-10

 

15.5

Real Time Clock.............................................................................................

15-13

 

 

15.5.1 RTC Registers and RAM...................................................................

15-14

 

 

15.5.2

RTC Update Cycle ............................................................................

15-17

 

 

15.5.3

RTC Interrupts...................................................................................

15-17

 

 

15.5.4

Lockable RAM Ranges .....................................................................

15-17

16

IFB Power Management ...............................................................................................

16-1

 

16.1

Overview ..........................................................................................................

16-1

 

16.2

IFB Power Planes ............................................................................................

16-2

 

 

16.2.1

Power Plane Descriptions ...................................................................

16-2

 

 

16.2.2

SMI# Generation .................................................................................

16-2

 

 

16.2.3

SCI Generation ...................................................................................

16-3

 

 

16.2.4

Sleep States........................................................................................

16-3

 

 

16.2.5 ACPI Bits Not Implemented by IFB .....................................................

16-4

 

 

16.2.6 Entry/Exit for the S4 and S5 States.....................................................

16-4

 

16.3

Handling of Power Failures in IFB....................................................................

16-5

Figures

 

 

 

 

 

1-1

Diagram of a Typical Intel® 460GX Chipset-based System with AGP ..............

1-1

 

4-1

System Memory Address Space........................................................................

4-2

 

4-2

Itanium™ Processor and Chipset-specific Memory Space ................................

4-5

 

4-3

System I/O Address Space ................................................................................

4-6

 

4-4

System Memory Address Space as Viewed from an Expander

 

 

 

Bridge (PXB/GXB)..............................................................................................

4-7

 

5-1

Maximum Memory Configuration Using Two Cards...........................................

5-2

 

5-2

Address Interleaving ..........................................................................................

5-4

 

6-1

SAC Error Flow on Data...................................................................................

6-14

 

6-2

SDC Error Data Flow .......................................................................................

6-15

 

6-3

GXB Error Flow ................................................................................................

6-25

 

7-1

GART Table Usage for 4k Pages.......................................................................

7-2

 

7-2

GART Table Usage for 4 MB Pages ..................................................................

7-2

 

7-3

GART Entry Format for 4kB Pages....................................................................

7-3

x

Intel® 460GX Chipset System Software Developer’s Manual