Page
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Contents
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Figures
Tables
Page
Introduction
1.1System Overview
1.1.1Component Overview
Table 1-1.Intel® 460GX Chipset Components
1.2Product Features
1.3Itanium™ Processor System Bus Support
1.4DRAM Interface Support
1.5I/O Support
1.6RAS Features
1.7Other Platform Components
1.8Reference Documents
1.9Revision History
Page
Register Descriptions
2.1Access Mechanism
2.2Access Restrictions
2.2.2Register Attributes
2.2.3Reserved Bits Defined in Registers
2.2.4Reserved or Undefined Register Locations
2.2.5Default Upon Reset
default
2.3I/O Mapped Registers
2.4Error Handling Registers
7Disable
6Valid
ITID
DEDTID: DED ITID
FSETID: FSE ITID
2.4.1.4FERR_SAC: First Error Status Register
31Memory Card B Error (MBE)
30Memory Card A Error (MAE)
29XSERR# Asserted (XSA)
28‘Store-Write’Command Underflow, card A, Stack L (SCAL)
18‘Completion’ Command Underflow; MAC B, Stack R (CCBR)
17BERR# Observed (BER)
16IOQ Underflow/Overflow (IUE)
15reserved(0)
14External XBINIT# Active. (XBE)
2.4.1.6SA_FERR: System Address on First Error
106LOCK, ’b’ phase
105ADS, ’b’ phase
104RP#, ’b’ phase. 103:99 REQ, ’b’ phase
98AP1; ’b’ phase
2.4.1.8BIUDATA: BIU Data Register
115:82 Address bits [35:2]
Reqa
DID
BE
2.4.2SDC
2.4.2.1SEC0_D_FERR: Data on First Memory Card B SEC
2.4.2.2SEC0_ECC_FERR: ECC on First Memory Card B SEC
2.4.2.3SEC0_TXINFO_FERR: TXINFO on First Memory Card B SEC
2.4.2.4DED0_D_FERR: Data on First Memory Card B DED
2.4.2.5DED0_ECC_FERR: ECC on First Memory Card B DED
2.4.2.6DED0_TXINFO_FERR: TXINFO on First Memory Card B DED
2.4.2.7SEC1_D_FERR: Data on First Memory Card A SEC
2.4.2.8SEC1_ECC_FERR: ECC on First Memory Card A SEC
2.4.2.9SEC1_TXINFO_FERR: TXINFO on First Memory Card A SEC
2.4.2.10DED1_D_FERR: Data on First Memory Card A DED
2.4.2.11DED1_ECC_FERR: ECC on First Memory Card A DED
2.4.2.12DED1_TXINFO_FERR: TXINFO on First Memory Card A DED
2.4.2.13SDC_FERR: First Error Status Register
30PDB Receive Length Error (RLE) Private Bus receive length error
29DRDY# Protocol Error (FS2)
26’Forward’ Overlapping ’Forward’; Card A (FWMDI1)
25’Load’ Overlapping ’Load’; Card A (LRMDI1)
24’Load’ Overlapping ’Forward’; Card A (WrRd1)
23’Forward’ Overlapping ’Load’; Card A (RdWr1)
22’Forward’ Underflow; Card A Right Stack Error (FR1)
5System Bus Double Bit Error (DEDF)
4System Bus Single Bit Error (SECF)
3SDC Card A Double Bit Error (DED1)
2SDC Card A Single Bit Error (SEC1)
1SDC Card B Double Bit Error (DED0)
2.4.2.17SDCRSP_FERR: Response on First SDCRSP Error
2.4.2.18DPBRLE_FERR: Private Data Bus Receive Length Error
2.4.2.19ECCMSK0: ECC Mask Register - Card B
ECC Generation Mask
2.4.2.20ECCMSK1: ECC Mask Register - Card A
2.4.2.21ECCMSKF: ECC Mask Register
2.4.2.22ParMskP: PB Parity Mask and IB Correction Enable Register
2.4.2.23PVD_D_FERR: Data on First PVD Parity Error
2.4.2.24PVD_PAR_FERR: Parity on First PVD Parity Error
2.4.2.25PVD_TXINFO_FERR: TXINFO on First PVD Parity Error
2.4.2.26SECF_D_FERR: Data on First System Bus SEC
2.4.2.27SECF_ECC_FERR: ECC on First System Bus SEC
2.4.2.28SECF_TXINFO_FERR: TXINFO on First System Bus SEC
2.4.2.29DEDF_D_FERR: Data on First System Bus DED
2.4.2.30DEDF_ECC_FERR: ECC on First System Bus DED
2.4.3MAC
2.4.3.1FERR_MAC: First Error Status Register
1Que-OverflowError
0Parity Error - CMND
2.4.3.2CMND_FERR: Command on First Error
2.4.4PXB
2.4.4.1ERRSTS: Error Status Register
6PERR# observed on PCI Bus
5Parity Error on Received PCI Data
4Parity Error on PCI Address
3Inbound Delayed Read Time-outFlag
1Performance Monitor #1 Event Flag
0Performance Monitor #0 Event Flag
2.4.4.2ERRCMD: Error Command Register
6Assert SERR# on Observed Parity Error
2.4.5GXB
FERR_GXB
2FERR_PCI bit asserted
1FERR_AGP bit asserted
0 FERR_GART bit asserted
5Lo-priorityRead Data Que Parity Error
4Hi-priorityRead Data Que Parity Error
3Use of Pipe with Sideband Enabled
2AGP address from graphics card [63:40] not equal to
1AGP Request Queue Overflow
2.4.5.6NERR_GART
2.4.5.7PAC_ERR: PCI Address & Cmd First Error
PCI Command
PCI Address
2.4.5.8PD_ERR: PCI Data First Error
2.4.6WXB
2.4.6.1ERRSTS: Error Status Register
power-good
7INTRQ Asserted Flag
6XBINIT Asserted Flag
2.4.6.2ERRCMD: Error Command Register
15XBINITO: XBinit Override Enable
13IRQE: INTRQ Enable
12ASAPE: Assert SERR# on Address Parity Error
11ASDPE: Assert SERR# on any Data Parity Error
7PCILV: PCI Error Logs Valid
6UMATA: Unexpected Master or Target Abort
5DTE: Discard Timer Expiration
4SES: System Error Signaled
3PODT: PERR# Observed on PCI Data Transfer
2.5Performance Monitor Registers
39Overflow
38:0 Count Value
IT_MON_PMC_[0 to 5]: Internal Transaction Performance Monitor Config. Register
40:33 Length Encodings
32:24 DMASK Encodings
23:15 UMASK Encodings
14:8 Event Select
6:5 Disable Source
4:3 Enable Source
2:0 Reload Control
2.5.2SDC
2.5.2.1FSB_D_PMC_[1,0]: System Bus Performance Monitor Configuration Register
Mask
14:8 Event Select
6:5 Disable Source
4:3 Enable Source
2:0 Reload Control
2.5.2.2FSB_D_PMD_[1,0]: System Bus Performance Monitor Data Registers
2.5.3PXB
2.5.3.1PMD[1:0]: Performance Monitoring Data Register
31:0 Count Value
2.5.3.2PMR[1:0]: Performance Monitoring Response
7:6 Interrupt Assertion
1:0 Reload Mode
2.5.3.3PME[1:0]: Performance Monitoring Event Selection
14Count Data Cycles
13:10 Initiating Agent Selection
9:8 Transaction Destination Selection
2.5.4GXB
2.5.4.1AGP_PMD_0,1: AGP Performance Monitor Data Registers
2.5.4.2PCI_PMD: PCI Performance Monitor Data Registers
2.5.4.3PERCON: Performance Monitor Control Register
1Event 1 Input
0Event 0 Input
2.5.4.4AGP_PMC_[0,1]: AGP Performance Monitor Configuration Register
QW (8 bytes). Used also for code 11 0000 00 - All events
17:16 Pipe or Sideband Request Mask
13:8 Event Select
7EVENT1 Count Enable
2.5.4.5PCI_PMC: PCI Performance Monitor Configuration Register
17:16 Initiating Agent
Page
2.5.5WXB
2.5.5.1PCI_WXB_PMC0: PCI Performance Monitor Configuration Register
23:21 Data Transfer and Transaction Qualifier
18:17 Issuing Agent Qualifier
16:11 Event Select
2.6Interrupt Related Registers
2.6.2PID PCI Memory-mappedRegisters
Table 2-2. Memory-MappedRegister Summary
2.6.2.1I/O Register Select Register (FEC00000h)
Table 2-3.I/O Select Register Format
2.6.2.2I/O Window Register (FEC00010h)
2.6.3PID Indirect Access Registers
2.6.3.1I/O (x)APIC ID Register (00h)
Table 2-6. Memory-mappedRegister Summary
Table 2-6. Memory-mappedRegister Summary (Cont’d)
Table 2-7.I/O APIC ID Register Format
2.6.3.2I/O (x)APIC Version Register (01h)
Table 2-8.I/O (x)APIC Version Register Format
2.6.3.3I/O (x)APIC Arbitration ID Register (02h)
Table 2-9.I/O (x)APIC Arbitration ID Register Format
2.6.3.4I/O (x)APIC RTE (10h-8Fh)
Table 2-10.I/O (x)APIC RTE Format
Table 2-10.I/O (x)APIC RTE Format (Cont’d)
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System Architecture
3.1Coherency
3.2Ordering
3.3Processor to PCI Traffic and PCI to PCI (Peer-to-Peer) Traffic
3.4WXB Arbitration
3.5Big-endianSupport
3.6Indivisible Operations
AGP LOCKS
3.6.2Inbound PCI Locks
3.6.3Atomic Writes
3.6.4Atomic Reads
3.6.5Locks with AGP Non-coherentTraffic
3.7Interrupt Delivery
3.8WXB PCI Hot-PlugSupport
3.8.1Slot Power-upand Enable
3.8.2Slot Power-downand Disable
Page
System Address Map
4.1Memory Map
Figure 4-1.System Memory Address Space
4.1.1.4System Firmware
4.1.2Low Extended Memory Region
4.1.3Medium Extended Memory Region
4.1.3.1Variable GAP
4.1.4High Extended Memory (above 4G)
4.1.5Re-mappedMemory Areas
4.2I/O Address Map
Figure 4-3.System I/O Address Space
4.3Devices View of the System Memory Map
4.4Legal and Illegal Address Disposition
Table 4-1.Address Disposition (Cont’d)
Page
Memory Subsystem
5.1Organization
Figure 5-1.Maximum Memory Configuration Using Two Cards
Table 5-2.Minimum/Maximum Memory Size per Configuration
5.1.1DIMM Types
5.2Interleaving/Configurations
5.3Bandwidth
5.4Memory Subsystem Clocking
5.5Supporting Features
5.5.3Hardware Initialization
5.5.4Memory Scrubbing
Table 5-4.Scrubbing Time
Page
Data Integrity and Error Handling
6.1Integrity
6.1.2DRAM
6.1.3Expander Buses
6.1.4PCI Buses
6.1.5AGP
6.1.6Private Bus between SAC and SDC
6.2Memory ECC Routing
6.3Data Poisoning
6.4Usage of First-errorand Next-error
6.4.1Masked Bits
6.4.2BERR#/BINIT# Generation
6.4.3INTREQ#
6.5SAC/SDC Errors
6.5.2System Bus Errors
6.5.3SAC to SDC Interface Errors
6.5.4SAC to MAC Interface Errors
6.5.5SDC/Memory Card Interface Errors
6.6Error Determination
6.6.1SAC Address on an Error
6.6.1.1Special Notes on Usage of SECTID, DEDTID, FSETID Registers
6.6.2SDC Logging Registers
6.7Clearing Errors
6.8Multiple Errors
6.8.1SDC Multiple Errors
6.8.2SAC Multiple Errors
6.8.3Single Errors with Multiple Reporting
6.8.4Error Anomalies
6.9Data Flow Errors
6.10Error Conditions
Table 6-1.Error Cases
Table 6-1.Error Cases (Cont’d)
Page
Page
6.11PCI Integrity
6.11.2.2Received Target Disconnect
6.11.2.3Received Target Retry
6.11.2.4Received Target Abort
6.11.2.5Data Parity Errors
6.11.3PXB as Target
6.11.3.1Target Disconnect
6.11.3.2Target Retry
6.11.3.3Target Abort
6.11.3.4Data Parity Errors
6.11.4GXB Error Flow
6.11.4.1.1 GXB_XBINIT#
6.11.4.1.2 XINTR#
6.11.4.2.1 PCI Interface Errors
6.11.4.2.2 GART Interface Errors
6.11.4.2.3 AGP Interface Errors
6.11.4.2.4 Data Errors
6.11.4.3Multiple Errors
Figure 6-3.GXB Error Flow
6.12WXB Data Integrity and Error Handling
6.12.4Error Mask Bits
6.12.5Error Steering/Signaling
Table 6-3.Supported Error Escalation to XBINIT#a
Table 6-4.Supported Error Escalation to SERR_OUT#a
Table 6-5.Supported Error Escalation to P(A/B)INTRQ#
6.12.5.1SERR# Generation
6.12.5.2XBINIT# Generation
6.12.6INTRQ# Interrupt
6.12.7Error Determination and Logging
may
6.12.8.1.1 Master Abort
6.12.8.1.2 Received Target Disconnect
6.12.8.1.3 Received Target Retry
6.12.8.1.4 Received Target Abort
6.12.8.1.5 Data Parity Errors
6.12.8.1.6 Other Violations
6.12.8.2.1 Illegal PCI Request Type
6.12.8.2.2 Target Disconnect
6.12.8.2.3 Target Retry
6.12.8.2.4 Target Abort
6.12.8.3PCI Interface Errors
•System Error Signaled
•Discard Timer Expiration
AGP Subsystem
7.1Graphics Address Relocation Table (GART)
Figure 7-1.GART Table Usage for 4k Pages
12b
24b
Figure 7-2.GART Table Usage for 4 MB Pages
22b
7.1.1GART Implementation
Figure 7-3.GART Entry Format for 4kB Pages
Figure 7-4.GART Entry Format for 4 MB Pages
7.1.1.1Page Sizes
7.1.1.2GTLB
7.1.2Programming GART
7.1.3GART Implementation
Figure 7-5.GART SRAM Timings
7.1.4Coherency
7.2AGP Traffic
7.2.2Traffic Priority
7.2.3Coherency, Translation and Types of AGP Traffic
Table 7-1.Coherency for AGP/PCI Streams
7.2.4Ordering Rules
7.2.5Processor Locks and AGP Traffic
7.2.6Address Alignment and Transfer Sizes
7.2.6.1Address Faults
7.2.7PCI Semantics Traffic
7.2.7.1Inbound Reads
Delayed Transactions
7.2.7.2PCI Stream Read Prefetching
7.2.7.3Inbound Reads Directed To Memory
7.2.7.4Inbound Delayed Read Matching Rules
Table 7-2.Delayed Read Matching Criteria
7.2.7.5Inbound I/O Reads
7.2.7.6Inbound Writes
Writes to Memory
7.2.7.7Inbound I/O Writes
7.2.7.8Retry/Disconnect Conditions
7.2.7.9Outbound Reads
7.2.7.10Outbound Writes
Write Combining
This holds true for all memory attributes, not just WC
7.3Bandwidth
7.4Latency
7.5GXB Address Map
Page
Page
WXB Hot-Plug
8.1IHPC Configuration Registers
Table 8-1.IHPC Configuration Register Space
8.1.1Page Number List for the IHPC PCI Register Descriptions
Page
8.1.2VID: Vendor Identification Register
15:0 Vendor Identification Number
8.1.3DID: Device Identification Register
8.1.4PCICMD: PCI Command Register
9Fast Back-to-BackEnable
8SERR# Enable
7Wait Cycle Control
6Parity Error Enable
8.1.5PCISTS: PCI Status Register
15Detected Parity Error
14Signaled System Error
13Received Master Abort
12Received Target Abort
8.1.7CLASS: Class Register
23:16 Base Class
15:8 Sub-Class
7:0 Register-levelProgramming Interface
8.1.8CLS: Cache Line Size
8.1.11Base Address
31:8 Base Address
7:4 Indicate 256-byteAddress Space Requested
3Not Prefetchable Hardwired Value
Type:
8.1.15Interrupt Pin
8.1.16Hot-PlugSlot Identifier
8.1.17Miscellaneous Hot-PlugConfiguration
8.1.18Hot-PlugFeatures
8.1.19Switch Change SERR Status
8.1.20Power Fault SERR Status
8.2IHPC Memory Mapped Registers
Table 8-2.IHPC Memor Mapped Register Space
8.2.1Page Number List for IHPC Memory Mapped Register Descriptions
8.2.2Slot Enable
5Enable Slot F
4Enable Slot E
3Enable Slot D
8.2.3Hot-PlugMiscellaneous
8.2.4LED Control
8.2.5Hot-PlugInterrupt Input and Clear
8.2.6Hot-PlugInterrupt Mask
8.2.7Serial Input Byte Data
8.2.8Serial Input Byte Pointer
8.2.9General Purpose Output
8.2.10Hot-Plug Non-interruptInputs
8.2.11Hot-PlugSlot Identifier
8.2.12Hot-PlugSwitch Interrupt Redirect Enable
8.2.13Slot Power Control
8.2.14Extended Hot-PlugMiscellaneous
IFB Register Mapping
9.1PCI / LPC / FWH Configuration
Page
9.2IDE Configuration
9.3Universal Serial Bus (USB) Configuration
9.4SMBus Controller Configuration
Page
IFB Usage Considerations
10.1Usage of 1MIN Timer in Power Management
10.2Usage of the SW SMI# Timer
10.3CD-ROMAUTO RUN Feature of the OS
10.4ACPI, SMBus, GPIO Base Address Reporting to the
10.5Ultra DMA Configuration
The Ultra DMA
The Ultra DMA Cycle Time Field
10.5.3Determining a Drive’s Transfer Rate Capabilities
10.5.3.1Overview
Table 10-1.Identify Device Information Used for Determining Drive Capabilities
Page
10.5.4Determining a Drive’s Best Ultra DMA Capability
Determining a Drive’s Best Multi Word DMA/Single Word DMA
Page
10.5.5.1Determining a Drive’s Best PIO Capability
Table 10-6.Drive PIO Capability as a Function of Cycle Time
10.5.6IFB Timing Settings
10.5.6.1DMA/PIO Timing Settings
Table 10-7.IFB Drive Mode Based on DMA/PIO Capabilities
Table 10-8.IDE Mode/Drive Feature Settings for Optimal DMA/PIO Operation
Table 10-9.DMA/PIO Timing Values Based on PIIX Cable Mode/System Speed
10.5.6.2Ultra DMA Timing Settings
Table 10-10.Ultra DMA Timing Value Based on Drive Mode
10.5.7Drive Configuration for Selected Timings
Table 10-11.Ultra DMA/Multi Word DMA/Single Word Transfer/Mode Values
Table 10-12.PIO Transfer/Mode Values
10.5.7.1BMIS1 - Bus Master IDE Status Register
(Primary: Bus Master IDE Base I/O Address + Offset 02h)
10.5.7.2BMIS2 - Bus Master IDE Status Register
10.5.8Settings Checklist
Table 10-13.Drive Capabilities Checklist
Table 10-14.IFB Settings Checklist
10.5.9Example Configurations
10.5.9.1Example #1: Ultra DMA/33 Configuration
10.5.9.2Example #2: Mixed Ultra DMA/33 and Non-ultraDMA/33 Configuration
10.5.9.3Example #3: Non Ultra DMA/33 Drive Configuration
10.5.10Ultra DMA System Software Considerations
10.5.11Additional Ultra DMA/PCI Bus Master IDE Device Driver Considerations
10.5.11.1Bus Master IDE Command and Status Register
10.5.11.2BMICX–BusMaster IDE Command Register (I/O)
10.5.11.3BMISX–BusMaster IDE Status Register (I/O)
10.6USB Resume Enable Bit
Page
LPC/FWH Interface Configuration
11.1PCI to LPC/FWH Interface Configuration Space Registers (PCI Function 0)
11.1.3PCICMD–PCICommand Register (Function 0)
11.1.4PCISTS–PCIDevice Status Register (Function 0)
11.1.5RID–RevisionIdentification Register (Function 0)
11.1.6CLASSC–ClassCode Register (Function 0)
11.1.7HEDT–HeaderType Register (Function 0)
11.1.8ACPI Base Address (Function 0)
11.1.9ACPI Enable (Function 0)
11.1.10SCI IRQ Routing Control
11.1.11BIOSEN–BIOSEnable Register (FUNCTION 0)
11.1.12PIRQRC[A:D]–PIRQxRoute Control Registers (Function 0)
11.1.13SerIRQC–SerialIRQ Control Register (Function 0)
11.1.14TOM–Topof Memory Register (Function 0)
11.1.15MSTAT–MiscellaneousStatus Register (Function 0)
11.1.16Deterministic Latency Control Register (Function 0)
11.1.17MGPIOC–MuxedGPIO Control (Function 0)
11.1.18PDMACFG–PCIDMA Configuration Resister (Function O)
11.1.19DDMABP–DistributedDMA Slave Base Pointer Registers (Function 0)
11.1.20RTCCFG–RealTime Clock Configuration Register (Function 0)
11.1.21GPIO Base Address (FUNCTION 0)
11.1.22GPIO Enable (FUNCTION 0)
11.1.23LPC COM Decode Ranges (Function 0)
11.1.24LPC FDD/LPT Decode Ranges (Function 0)
11.1.25LPC Sound Decode Ranges (Function 0)
11.1.26LPC Generic Decode Range (Function 0)
11.1.27LPC Enables (Function 0)
11.1.27.1Firmware Hub (FWH) Decode Enable Register
11.1.27.2Firmware Hub (FWH) Select Register
11.2PCI to LPC I/O Space Registers
11.2.1.2Dcm–DmaChannel Mode Register (I/O)
11.2.1.3Dr–DmaRequest Register (I/O)
11.2.1.4WSMB–WriteSingle Mask Bit (I/O)
11.2.1.5RWAMB–Read /Write All Mask Bits (I/O)
11.2.1.6Ds–DmaStatus Register (I/O)
11.2.1.7DBADDR–DMABase and Current Address Registers (I/O)
11.2.1.8DBCNT–DmaBase and Current Count Registers (I/O)
11.2.1.9DLPAGE–DMALow Page Registers (I/O)
11.2.1.10DCBP–DmaClear Byte Pointer Register (I/O)
11.2.1.11Dmc–DmaMaster Clear Register (I/O)
11.2.1.12Dclm–DmaClear Mask Register (I/O)
11.2.2Interrupt Controller Registers
11.2.2.1Icw1–InitializationCommand Word 1 Register (I/O)
11.2.2.2Icw2–InitializationCommand Word 2 Register (I/O)
11.2.2.3Icw3–InitializationCommand Word 3 Register (I/O)
11.2.2.4Icw3–InitializationCommand Word 3 Register (I/O)
11.2.2.5Icw4–InitializationCommand Word 4 Register (I/O)
11.2.2.6Ocw1–OperationalControl Word 1 Register (I/O)
11.2.2.7Ocw2–OperationalControl Word 2 Register (I/O)
11.2.2.8Ocw3–OperationalControl Word 3 Register (I/O)
11.2.2.9Elcr1–Edge/LevelControl Register (I/O)
11.2.2.10Elcr2–Edge/LevelControl Register (I/O)
11.2.3Counter/Timer Registers
11.2.3.1Tcw–TimerControl Word Register (I/O)
Read Back Command
Counter Latch Command
11.2.3.2TMRSTS–TimerStatus Registers (I/O)
11.2.3.3TMRCNT–TimerCount Registers (I/O)
11.2.4NMI Registers
11.2.4.1Nmisc–NmiStatus and Control Register (I/O)
NmiEN–Nmi
11.2.5Real Time Clock Registers
RTCI–Real-time
11.2.5.2RTCD–Real-timeClock Data Register (I/O)
11.2.5.3RTCEI–Real-timeClock Extended Index Register (I/O)
11.2.5.4RTCED–Real-timeClock Extended Data Register (I/O)
11.2.6Advanced Power Management (APM) Registers
11.2.6.1APMC–AdvancedPower Management Control Port (I/O)
11.2.6.2APMS–AdvancedPower Management Status Port (I/O)
11.2.7ACPI Registers
11.2.7.1Power Management 1 Status
11.2.7.2Power Management 1 Enable
11.2.7.3Power Management 1 Control
11.2.7.4Power Management 1 Timer
11.2.7.5General Purpose 0 Status
11.2.7.6General Purpose 0 Enable
11.2.7.7General Purpose 1 Status
11.2.7.8General Purpose 1 Enable
11.2.8SMI Registers
11.2.8.1Global Control and Enable
11.2.8.2Global Status Register
11.2.9General Purpose I/O Registers
11.2.9.1GP Output
GP Data
11.2.9.3GP TTL
GP Blink
11.2.9.5GP Lock
GP Invert
GP SMI
GP Pulse
GP Core
11.2.9.10GP Pull-up
Page
IDE Configuration
12.1PCI Configuration Registers (Function 1)
12.2IDE Controller Register Descriptions (PCI Function 1)
12.2.1VID–VendorIdentification Register (Function 1)
12.2.2DID–DeviceIdentification Register (Function 1)
12.2.3PCICMD–PCICommand Register (Function 1)
12.2.4PCISTS–PCIDevice Status Register (Function 1)
12.2.5CLASSC–ClassCode Register (Function 1)
12.2.6MLT–MasterLatency Timer Register (Function 1)
12.2.7BMIBA–BusMaster Interface Base Address Register (Function 1)
12.2.8SVID–SubsystemVendor ID (Function 1)
12.2.9SID–SubsystemID (Function 1)
12.2.10IDETIM–IDETiming Register (Function 1)
12.2.11SIDETIM–SlaveIDE Timing Register (Function 1)
12.2.12DMACTL–SynchronousDMA Control Register (Function 1)
12.2.13SDMATIM–SynchronousDMA Timing Register (Function 1)
12.3IDE Controller I/O Space Registers
12.3.2BMISx–BusMaster IDE Status Register (I/O)
Table 12-4.Interrupt/Activity Status Combinations
12.3.3BMIDTPx–BusMaster IDE Descriptor Table Pointer Register (I/O)
Page
Universal Serial Bus (USB)
Configuration
13.1PCI Configuration Registers (Function 2)
13.2USB Host Controller Register Descriptions (PCI Function 2)
13.2.4PCISTS–PCIDevice Status Register (Function 2)
13.2.5RID–RevisionIdentification Register (Function 2)
13.2.6CLASSC–ClassCode Register (Function 2)
13.2.7MLT–MasterLatency Timer Register (Function 2)
13.2.8HEDT–HeaderType Register (Function 2)
13.2.9USBBA–USBI/O Space Base Address (Function 2)
13.2.10SVID–SubsystemVendor ID (Function 2)
13.2.11SID–SubsystemID (Function 2)
13.2.12INTLN–InterruptLine Register (Function 2)
13.2.13INTPN–InterruptPin (Function 2)
13.2.14Miscellaneous Control (Function 2)
13.2.15SBRNUM–SerialBus Release Number (Function 2)
13.2.16LEGSUP–LegacySupport Register (Function 2)
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13.3USB Host Controller I/O Space Registers
Table 13-2.Run/Stop, Debug Bit Interaction
13.3.2USBSTS–USBStatus Register (I/O)
13.3.3USBINTR–USBInterrupt Enable Register (I/O)
13.3.4FRNUM–FrameNumber Register (I/O)
13.3.5FLBASEADD–FrameList Base Address Register (I/O)
13.3.6SOFMOD–Startof Frame (SOF) Modify Register (I/O)
13.3.7PORTSC–PortStatus and Control Register (I/O)
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SM Bus Controller Configuration
14.1SM Bus Configuration Registers (Function 3)
14.2System Management Register Descriptions
14.2.4PCISTS–PCIDevice Status Register (Function 3)
14.2.5RID–RevisionIdentification Register (Function 3)
14.2.6CLASSC–ClassCode Register (Function 3)
14.2.7SMBBA–SMBusBase Address (Function 3)
14.2.8SVID–SubsystemVendor ID (Function 3)
14.2.9SID–SubsystemID (Function 3)
14.2.10INTLN–InterruptLine Register (Function 3)
14.2.11INTPN–InterruptPin (Function 3)
14.2.12Host Configuration
14.3SMBus I/O Space Registers
14.3.1smbhststs–SMBusHost Status Register (I/O)
14.3.2smbslvsts–SMBusSlave Status Register (I/O)
14.3.3smbhstcnt–SMBusHost Control Register (I/O)
14.3.4smbhstcmd–SMBusHost Command Register (I/O)
14.3.5smbhstadd–SMBusHost Address Register (I/O)
14.3.6smbhstdat0–SMBusHost Data 0 Register (I/O)
14.3.7smbhstdat1–SMBusHost Data 1 Register (I/O)
14.3.8smbblkdat–SMBusBlock Data Register (I/O)
14.3.9smbslvcnt–SMBusSlave Control Register (I/O)
14.3.9.1 10.3.10.smbshdwcmd–SMBusShadow Command Register (I/O)
14.3.9.210.3.11.smbslvevt–SMBusSlave Event Register (I/O)
14.3.10smbslvdat–SMBusSlave Data Register (I/O)
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PCI/LPC Bridge Description
15.1PCI Interface
15.2Interrupt Controller
15.2.1Programming the Interrupt Controller
15.2.1.1Initialization Command Words (ICWs)
15.2.1.2Operation Command Words (OCWs)
15.2.2End of Interrupt Operation
15.2.2.1End of Interrupt (EOI)
15.2.2.2Automatic End of Interrupt (AEOI) Mode
15.2.3Modes of Operation
15.2.3.1Fully Nested Mode
15.2.3.2The Special Fully Nested Mode
15.2.3.3Automatic Rotation (Equal Priority Devices)
15.2.3.4Specific Rotation (Specific Priority)
15.2.4Cascade Mode
15.2.5Edge and Level Triggered Mode
15.2.6Interrupt Masks
15.2.6.1Masking on an Individual Interrupt Request Basis
15.2.6.2Special Mask Mode
15.2.7Reading the Interrupt Controller Status
15.2.8Interrupt Steering
15.3Serial Interrupts
Table 15-1.SERIRQ Frames
15.3.1.4Stop Frame
15.4Timer/Counters
15.4.1.1Write Operations
15.4.1.2Interval Timer Control Word Format
15.4.1.3Read Operations
15.4.1.4Counter I/O Port Read
15.4.1.5Counter Latch Command
15.5Real Time Clock
15.5.1RTC Registers and RAM
Table 15-2.RTC (Standard) RAM Bank
Register A
Register B
Register C
Register D
15.5.2RTC Update Cycle
15.5.3RTC Interrupts
15.5.4Lockable RAM Ranges
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IFB Power Management
16.1Overview
16.2IFB Power Planes
16.2.3SCI Generation
Table 16-3.Causes of SCI#
16.2.4Sleep States
16.2.5ACPI Bits Not Implemented by IFB
Table 16-4.ACPI Bits Not Implemented in IFB
16.2.6Entry/Exit for the S4 and S5 States
16.3Handling of Power Failures in IFB
