Intel 460GX manual Tables

7-4	GART Entry Format for 4 MB Pages..................................................................	7-3
7-5	GART SRAM Timings ........................................................................................	7-5

Tables

1-1	Intel® 460GX Chipset Components ...................................................................	1-2
2-1	Device Mapping on Bus CBN.............................................................................	2-2
2-2	Memory-Mapped Register Summary ...............................................................	2-45
2-3	I/O Select Register Format...............................................................................	2-45
2-4	I/O Window Register Format ............................................................................	2-46
2-5	(x)APIC EOI Register Format...........................................................................	2-46
2-6	Memory-mapped Register Summary ...............................................................	2-47
2-7	I/O APIC ID Register Format............................................................................	2-49
2-8	I/O (x)APIC Version Register Format ...............................................................	2-49
2-9	I/O (x)APIC Arbitration ID Register Format ......................................................	2-50
2-10	I/O (x)APIC RTE Format ..................................................................................	2-50
4-1	Address Disposition............................................................................................	4-8
5-1	General Memory Characteristics........................................................................	5-1
5-2	Minimum/Maximum Memory Size per Configuration..........................................	5-3
5-3	Required DRAM Parameters..............................................................................	5-6
5-4	Scrubbing Time ..................................................................................................	5-7
6-1	Error Cases ......................................................................................................	6-16
6-2	List of WXB Error Sources Selectively Routable to XBINIT#, SERR_OUT#,
	and P(A/B)INTRQ#...........................................................................................	6-27
6-3	Supported Error Escalation to XBINIT#............................................................	6-27
6-4	Supported Error Escalation to SERR_OUT#....................................................	6-28
6-5	Supported Error Escalation to P(A/B)INTRQ# .................................................	6-28
7-1	Coherency for AGP/PCI Streams.......................................................................	7-8
7-2	Delayed Read Matching Criteria ......................................................................	7-11
7-3	Burst Write Combining Modes..........................................................................	7-13
7-4	Burst Write Combining Examples with 3 Writes in 1X Transfer Mode .............	7-13
7-5	Bandwidth Estimates for Various Request Sizes .............................................	7-14
8-1	IHPC Configuration Register Space...................................................................	8-2
8-2	IHPC Memor Mapped Register Space .............................................................	8-11
9-1	PCI Configuration Registers–Function 0(PCI to LPC/FWH Interface Bridge) ....	9-1
9-2	PCI Configuration Registers–Function 1 (IDE Interface)....................................	9-3
9-3	PCI Configuration Registers–Function 2 (USB Interface) ..................................	9-4
9-4	PCI Configuration Registers–Function 3 (SMBus Controller Interface) .............	9-5
10-1	Identify Device Information Used for Determining Drive Capabilities...............	10-3
10-2	Identify Device Information Used for Determining Ultra DMA
	Drive Capabilities .............................................................................................	10-5
10-3	Identify Device Information Used for Determining Multi/Single Word DMA
	Drive Capabilities .............................................................................................	10-6
10-4	Drive Multi Word DMA/Single Word DMA Capability as a Function
	of Cycle Time ...................................................................................................	10-7
10-5	Identify Device Information Used for Determining PIO Drive Capabilities........	10-8
10-6	Drive PIO Capability as a Function of Cycle Time ...........................................	10-8
10-7	IFB Drive Mode Based on DMA/PIO Capabilities ............................................	10-9
10-8	IDE Mode/Drive Feature Settings for Optimal DMA/PIO Operation ...............	10-10
10-9	DMA/PIO Timing Values Based on PIIX Cable Mode/System Speed............	10-11

Intel® 460GX Chipset System Software Developer’s Manual xi