I/O Address Map | Intel 460GX manual

System Address Map

Figure 4-2. Itanium™ Processor and Chipset-specific Memory Space

FFFF_FFFF

FF00_0000

FEC0_0000

FE00_0000

System Firmware

16 MB

Processor Specific

4 MB

Chipset Specific

12 MB

I/O reserved

1 MB

Interrupt Delivery

On system bus - 1MB

I/O reserved

1 MB

I/O SAPIC #255

I/O SAPIC #3 to # 254 4KB each

I/O SAPIC #2

I/O SAPIC #1

I/O SAPIC #0

Chipset

Reserved

8 MB

GART Table

2 MB

Chipset

Reserved

2 MB

FEFF_FFFF

FEF0_0000

FEE0_0000

FED0_0000

FECF_F000

FEC0_3000

FEC0_2000

FEC0_1000

FEC0_0000

FEBF_FFFF

FE60_0000

FE40_0000

FE20_0000

FE00_0000

PCI Bus mapping of SAPIC addresses.

PCI Bus 2A

PCI Bus 1A

PCI Bus 0B

PCI Bus 0A

4.2I/O Address Map

The 460GX chipset allows I/O addresses to be mapped to resources supported on the I/O buses underneath the 460GX chipset controller. This I/O space is partitioned into sixteen 4K byte segments. Each of the segments can be individually configured to any I/O bus. Segment 0 is always assigned to the compatibility I/O bus (of which there is only one per system).

There are four classes of I/O addresses that are specifically decoded by the 460GX chipset:

•All I/O addresses less than 100h: These addresses are specifically decoded as “defer-only” addresses. The SAC does not post any I/O accesses to this range, regardless of the state of the I/O posting enable bit. This is necessary because I/O accesses below 100h have historically had ordering side effects: e.g. accesses to the 8259 Interrupt Masks.

Intel® 460GX Chipset Software Developer’s Manual

4-5

Image 85

Intel 460GX manual I/O Address Map, Itanium Processor and Chipset-specific Memory Space

Contents

Intel 460GX Chipset System Software Developer’s Manual Intel 460GX Chipset System Software Developer’s Manual Contents Coherency 10.1 Latency 10-1 11-8 13.2.4 Figures Tables 12-11 System Overview Introduction Intel 460GX Chipset Components Component OverviewName Function Itanium Processor System Bus Support Product Features Dram Interface Support PXB FeaturesI/O Support GXB Features RAS Features Reference Documents Other Platform Components1 I/O & Firmware Bridge IFB Programmable Interrupt Device PID Date Description June Initial release Revision History Introduction Register Descriptions Access Mechanism Partitioning Access RestrictionsDevice Mapping on Bus CBN Device Register Attributes Default Upon ResetReserved Bits Defined in Registers Reserved or Undefined Register Locations I/O Mapped Registers Configaddress Configuration Address RegisterConsistency Gart Programming Region Configdata Configuration Data Register Error Handling Registers1 SAC 1.1 1.2 Bits Description Disable1.3 Valid Ferrsac First Error Status Register Nerrsac All Error Status Register Biuitid BIU Itid Register Saferr System Address on First Error Address bits Biudata BIU Data Register 2.1 SEC0DFERR Data on First Memory Card B SEC 2 SDC2.2 SEC0ECCFERR ECC on First Memory Card B SEC 2.3 SEC0TXINFOFERR Txinfo on First Memory Card B SEC 2.5 DED0ECCFERR ECC on First Memory Card B DED 2.4 DED0DFERR Data on First Memory Card B DED2.6 DED0TXINFOFERR Txinfo on First Memory Card B DED 2.7 SEC1DFERR Data on First Memory Card a SEC 2.9 SEC1TXINFOFERR Txinfo on First Memory Card a SEC 2.8 SEC1ECCFERR ECC on First Memory Card a SEC2.10 DED1DFERR Data on First Memory Card a DED 2.11 DED1ECCFERR ECC on First Memory Card a DED Sdcferr First Error Status Register2.12 DED1TXINFOFERR Txinfo on First Memory Card a DED 21 ’Forward’ Underflow Card a Left Stack Error FL1 22 ’Forward’ Underflow Card a Right Stack Error FR115 ’Forward’ Underflow Card B Right Stack Error FR0 14 ’Forward’ Underflow Card B Left Stack Error FL0 Pcmdferr Command on First Pcmd Parity Error Sdcnerr SDC Next Error Status RegisterPitidferr Data on First Pitid Parity Error Dpbrleferr Private Data Bus Receive Length Error Sdcrspferr Response on First Sdcrsp ErrorECCMSK0 ECC Mask Register Card B ECCMSK1 ECC Mask Register Card a ParMskP PB Parity Mask and IB Correction Enable RegisterEccmskf ECC Mask Register Pvdparferr Parity on First PVD Parity Error Pvddferr Data on First PVD Parity ErrorPvdtxinfoferr Txinfo on First PVD Parity Error Secfeccferr ECC on First System Bus SEC Secfdferr Data on First System Bus SECSecftxinfoferr Txinfo on First System Bus SEC Dedfdferr Data on First System Bus DED Que-Overflow Error Ferrmac First Error Status Register3 MAC Dedfeccferr ECC on First System Bus DED Errsts Error Status Register Cmndferr Command on First Error4 PXB Errcmd Error Command Register 5 GXB Ferragp First Error Status Register for AGP5.1 Ferrpci Nerragp Next Errors Status Register for AGP Ferrgart First Error Status Register for Gart Pderr PCI Data First Error Pacerr PCI Address & Cmd First ErrorNerrgart Fepci Register Records an PCI Bus Error Flag Nepci Register Records an PCI Bus Error Flag6 WXB Bits Description Intrq Asserted Flag Fepci PCI Bus First Error Status Register Nepci PCI Bus Next Error Status Register Fepcidl PCI First Error Data Log Fepcial PCI First Error Address/Command LogPerformance Monitor Registers 6764 C/BE30 6332 AD6332 310 AD310 Count Value OverflowLength Encodings Dmask Encodings Event Select Umask Encodings Enable Source Disable SourceReload Control 2 SDC FSBDPMD1,0 System Bus Performance Monitor Data Registers 3.1 PMD10 Performance Monitoring Data Register 3 PXB3.2 PMR10 Performance Monitoring Response 3.3 PME10 Performance Monitoring Event Selection Reload ModeCount Data Cycles Initiating Agent Selection AGPPMD0,1 AGP Performance Monitor Data Registers 4 GXB Percon Performance Monitor Control Register Pcipmd PCI Performance Monitor Data RegistersEvent 1 Input Event 0 Input AGPPMC0,1 AGP Performance Monitor Configuration RegisterPipe or Sideband Request Mask EVENT1 Count Enable Pcipmc PCI Performance Monitor Configuration RegisterInitiating Agent Disable Source 5 WXB PCIWXBPMC0 PCI Performance Monitor Configuration RegisterData Transfer and Transaction Qualifier Issuing Agent Qualifier Interrupt Related Registers PCIWXBPMC1 PCI Performance Monitor Configuration RegisterXtprs External Task Priority Registers PID PCI Memory-mapped Registers Address Name Access Default Value2.1 I/O Register Select Register FEC00000h Memory-Mapped Register Summary 2.2 I/O Window Register FEC00010h PID Indirect Access RegistersXAPIC EOI Register FEC00040h I/O Window Register Format 3.1 I/O xAPIC ID Register 00h Offset Name Access Default ValueRTE Memory-mapped Register Summary Cont’d 3.3 I/O xAPIC Arbitration ID Register 02h 3.2 I/O xAPIC Version Register 01hI/O Apic ID Register Format I/O xAPIC Version Register Format 3.4 I/O xAPIC RTE 10h-8Fh Bits Sapic Mode Apic Mode Description NameI/O xAPIC Arbitration ID Register Format 10. I/O xAPIC RTE Format 10. I/O xAPIC RTE Format Cont’d Sapic Mode Apic Mode Description Name Vector Destination Coherency System ArchitectureProcessor Coherency PCI Coherency OrderingAGP Coherency WXB Arbitration at the PCI Bus WXB ArbitrationArbitration for Inbound Transactions Indivisible Operations Big-endian SupportProcessor Locks Arbitration for Outbound Transactions Atomic Writes Inbound PCI LocksAtomic Reads Locks with AGP Non-coherent Traffic WXB PCI Hot-Plug Support Interrupt Delivery Slot Power-down and Disable Slot Power-up and Enable System Architecture Memory Map System Address MapCompatibility Region System Memory Address Space System Firmware Medium Extended Memory Region Low Extended Memory Region Re-mapped Memory Areas High Extended Memory above 4GVariable GAP Itanium Processor and Chipset-specific Memory Space I/O Address Map System I/O Address Space High PXB must ignore GXB must BINIT# after Gart Devices View of the System Memory Map Address Disposition Legal and Illegal Address DispositionAddress Range Outbound Inbound Dest. Decision Main memory if present above 4 GB Address Disposition Cont’dAbove TOM Binit System Address Map Memory Subsystem General Memory CharacteristicsOrganization System Maximum Memory Configuration Using Two Cards Technology & Configuration Size Minimum/Maximum Memory Size per ConfigurationDimm Types Double Number Memory Size Address Interleaving Interleaving/Configurations Non-uniform Memory Configurations Summary of Configuration RulesBandwidth Memory Subsystem Clocking Supporting FeaturesAuto Detection Removing a Bad Row Memory Scrubbing Hardware InitializationScrubbing Time Memory Size Time to Scrub Memory Subsystem Integrity Data Integrity and Error HandlingSystem Bus Expander Buses DramPCI Buses 5 AGP Memory ECC Routing Usage of First-error and Next-errorData Poisoning BERR#/BINIT# Generation Masked BitsINTREQ# Data ECC or Parity Errors SAC/SDC ErrorsXBINIT# XSERR# SAC to SDC Interface Errors System Bus Errors 5 SDC/Memory Card Interface Errors SAC to MAC Interface Errors 6 SDC/System Bus Errors Error DeterminationSDC Internal Errors SAC Address on an Error Special Notes on Usage of SECTID, DEDTID, Fsetid Registers SDC Logging Registers Multiple Errors Clearing Errors1 SAC/SDC Error Clearing ERR ERR SDC Multiple Errors Single Errors with Multiple Reporting SAC Multiple ErrorsError Anomalies SAC Error Flow on Data Data Flow Errors Table of Errors Error Conditions SAC to SDC Interface Errors Error CasesSystem Bus ADD/CMND Error Cases Cont’d Internal SDC Error Detected as PCI Master PXB Errors PCI Bus Monitoring PCI IntegrityPXB as Master Master Abort PXB as Target Target Retry GXB Error FlowTarget Abort GXB Errors GXB Error Signals Gart Interface Errors GXB Error Flow Multiple Errors Usage of First Error and Next Error Registers WXB Data Integrity and Error HandlingIntegrity Data Parity Poisoning Error Steering/Signaling Error Mask BitsSupported Error Escalation to XBINIT#a Abbreviation Error Supported Error Escalation to PA/BINTRQ# Supported Error Escalation to SERROUT#aSERR# Generation Escalation INTRQ# Interrupt Error Determination and LoggingXBINIT# Generation WXB as Bus Master Error Conditions Other Violations WXB as Target System Error Signaled PCI Interface ErrorsDiscard Timer Expiration Graphics Address Relocation Table Gart AGP Subsystem 24b 12b22b 14b Gart Entry Format for 4kB Pages Gart Implementation Sizes Programming GartGtlb Parity SGW# CoherencySE2 ADSC# ADSP# ADV# LBO# SB# SW# AGP Traffic 4.1 3.3V AGP 1X and 2X Mode CompatibilityInterrupt Handling Addresses Used by the Graphics Card Coherency, Translation and Types of AGP Traffic Traffic Priority Processor Locks and AGP Traffic Ordering RulesCoherency for AGP/PCI Streams Address Alignment and Transfer Sizes Address FaultsPCI Semantics Traffic Inbound Reads PCI Stream Read Prefetching Inbound Delayed Read Matching RulesInbound Reads Directed To Memory Command Address BEs Delayed Read Matching CriteriaInbound I/O Reads Inbound Writes Outbound Reads Retry/Disconnect ConditionsOutbound Writes Fast Back-to-Back Transactions Transfer Data Length Combining Supported Used ModeBurst Write Combining Modes 1st write 2nd write 3rd write Transferred as GXB Address Map LatencyInbound Read Prefetching Bandwidth Estimates for Various Request Sizes AGP Subsystem AGP Subsystem WXB Hot-Plug Ihpc Configuration Registers Ihpc Configuration Register Space VID Vendor Identification Register Number List for the Ihpc PCI Register DescriptionsDid Device Identification Register Pcicmd PCI Command Register RID Revision Identification Register Pcists PCI Status Register Class Class Register MLT Master Latency Timer RegisterCLS Cache Line Size HDR Header Register Svid Subsystem Vendor Identification Base AddressSID Subsystem ID Interrupt Line Interrupt Pin Miscellaneous Hot-Plug ConfigurationHot-Plug Slot Identifier Switch Change Serr Status Hot-Plug FeaturesPower Fault Serr Status Memory Mapped Register Access Port Memory Access IndexIhpc Memory Mapped Registers Arbiter Serr Status M66EN Ihpc Memor Mapped Register Space Number List for Ihpc Memory Mapped Register Descriptions Slot Enable LED Control Hot-Plug Miscellaneous Hot-Plug Interrupt Input and Clear Hot-Plug Interrupt Mask Serial Input Byte Data General Purpose Output Serial Input Byte PointerHot-Plug Non-interrupt Inputs Slot Power Control Hot-Plug Switch Interrupt Redirect EnableExtended Hot-Plug Miscellaneous PCI Configuration Registers Function PCI / LPC / FWH ConfigurationMnemonic Register Register Access IFB Register Mapping Pcists BiosenClassc Hedt PCI Configuration Registers-Function 1 IDE Interface IDE Configuration PCI Configuration Registers-Function 2 USB Interface Universal Serial Bus USB ConfigurationConfiguration Offset Mnemonic Register SMBus Configuration Registers Function SMBus Controller Configuration IFB Register Mapping Usage of the SW SMI# Timer Usage of 1MIN Timer in Power ManagementCD-ROM Auto RUN Feature of the OS IFB Usage Considerations Reserved Secondary Primary Drive Ultra DMA Mode Enable Ultra DMA ConfigurationDisabled Enabled SSDE1 SSDE0 PSDE1 PSDE0 Overview Determining a Drive’s Transfer Rate CapabilitiesCapability Word Bits Field Offset Ultra DMA Fields that Indicate Ultra DMA Drive Capabilities DMA Capability Word BitsPIO Capability Word Bits Field Determining a Drive’s Best Ultra DMA Capability 150 Minimum Multi Word DMA Transfer Cycle Time per Capability Word Offset Bits Field10-6 Determining a Drive’s Best PIO Capability Drives Reported DMA Drive’s Best DMA Mode Cycle Time Drive PIO Capability as a Function of Cycle Time Drives Reported PIO Drive’s Best PIO Mode 10.5.6.1 DMA/PIO Timing Settings IFB Timing SettingsIFB Drive Mode Based on DMA/PIO Capabilities Mode Yes Disabled Enabled DMA Mode Iordy If fixed disk DMA Iordy IDE Ultra DMA Timing Settings Drive Configuration for Selected Timings10. Ultra DMA Timing Value Based on Drive Mode DMA/PIO Timing Values Based on Piix Cable Mode/System Speed Drive’s Selected PIO Speed Capability 12. PIO Transfer/Mode Values10-12 13. Drive Capabilities Checklist Settings Checklist Example #1 Ultra DMA/33 Configuration Example Configurations14. IFB Settings Checklist Register Type Offset Value Comments 40-41h E377h Mode config. for Primary IDE Timing Register Example #3 Non Ultra DMA/33 Drive Configuration4A-4Bh 0002h Ultra DMA mode config 44h 0Bh Ultra DMA Control Register 4A-4Bh 0000h Ultra DMA System Software Considerations10-16 Intel 460GX Chipset Software Developer’s Manual 10-17 BMISX-Bus Master IDE Status Register I/O Bit Description Reserved. This bit is hardwired toBit Description Completed or halted Bit Type Description USB Resume Enable Bit 10-20 VID-Vendor Identification Register Function LPC/FWH Interface ConfigurationDID-Device Identification Register Function PCISTS-PCI Device Status Register Function PCICMD-PCI Command Register Function CLASSC-Class Code Register Function RID-Revision Identification Register FunctionHEDT-Header Type Register Function Bit Acpi Base Address Function Acpi Enable FunctionSCI IRQ Routing Control PIRQRCAD-PIRQx Route Control Registers Function BIOSEN-BIOS Enable Register Function TOM-Top of Memory Register Function SerIRQC-Serial IRQ Control Register Function Deterministic Latency Control Register Function MSTAT-Miscellaneous Status Register Function MGPIOC-Muxed Gpio Control Function PDMACFG-PCI DMA Configuration Resister Function OBits Description Base Offset Channel RTCCFG-Real Time Clock Configuration Register Function Gpio Base Address Function Gpio Enable FunctionLPC COM Decode Ranges Function Bits Decode Range 000 LPC FDD/LPT Decode Ranges Function011 110 LPC Generic Decode Range Function LPC Sound Decode Ranges Function220 233 240 253 260 273 280 293 11-12 Firmware Hub FWH Decode Enable Register LPC Enables FunctionReserved. This bit must be a 1413 Reserved Firmware Hub FWH Select Register Dcom-Dma Command Register I/O Test Mode RegisterPCI to LPC I/O Space Registers DMA Registers Dr-Dma Request Register I/O Dcm-Dma Channel Mode Register I/O RWAMB-Read / Write All Mask Bits I/O WSMB-Write Single Mask Bit I/OBit Description Reserved. Must be DBADDR-DMA Base and Current Address Registers I/O Ds-Dma Status Register I/O DBCNT-Dma Base and Current Count Registers I/O When counting down a DMA transferDLPAGE-DMA Low Page Registers I/O DCBP-Dma Clear Byte Pointer Register I/O Interrupt Controller Registers 11.2.2.1 Icw1-Initialization Command Word 1 Register I/ODmc-Dma Master Clear Register I/O Dclm-Dma Clear Mask Register I/O 11.2.2.3 Icw3-Initialization Command Word 3 Register I/O 11.2.2.2 Icw2-Initialization Command Word 2 Register I/OBit Description Reserved. Must be programmed to all 0s 11.2.2.5 Icw4-Initialization Command Word 4 Register I/O 11.2.2.4 Icw3-Initialization Command Word 3 Register I/O11.2.2.6 Ocw1-Operational Control Word 1 Register I/O 11-22 11.2.2.8 Ocw3-Operational Control Word 3 Register I/O 11.2.2.7 Ocw2-Operational Control Word 2 Register I/O Elcr1-Edge/Level Control Register I/O Tcw-Timer Control Word Register I/O Counter/Timer RegistersElcr2-Edge/Level Control Register I/O Bit Decription 5. When bit 3=0, status and/or count will not be latched Latched. When bit 4=1, the status will not be latched5. When bit 2=0, status and/or count will not be latched 5. When bit 1=0, status and/or count will not be latched TMRCNT-Timer Count Registers I/O TMRSTS-Timer Status Registers I/O Nmisc-Nmi Status and Control Register I/O NMI Registers Real Time Clock Registers NMI Enable. Used by IFB NMI logicRTCD-Real-time Clock Data Register I/O Used for NMI enabling/disabling. See description in Section APMC-Advanced Power Management Control Port I/O Advanced Power Management APM RegistersRTCEI-Real-time Clock Extended Index Register I/O RTCED-Real-time Clock Extended Data Register I/O Power Management 1 Status APMS-Advanced Power Management Status Port I/OAcpi Registers Power Management 1 Control Power Management 1 EnableStates can be supported in external logic 11-32 Bit Description Bits Mode Power Management 1 TimerGeneral Purpose 0 Status 3124 Reserved 230 Power up, this bit is set to ‘1’ General Purpose 0 Enable1512 Reserved CF9 write SMI Registers General Purpose 1 EnableGeneral Purpose 1 Status Port at B2h in I/O space Global Control and EnableStatus Register is set Thrmsts bit Global Status Register General Purpose I/O RegistersGPIO8 GPIO7 GP Data GP Output 1916 GP TTL159 Reserved Bit is set GP Lock GP BlinkGP Invert GP Pulse GP SMIGP Core GP Pull-up 11-42 PCI Configuration Registers Function IDE ConfigurationConfiguration Mnemonic Register IDE Controller Register Descriptions PCI Function Wait Cycle Control. This bit is hardwired to SERR# Enable. This bit is hardwired toParity Error Response. This bit is hardwired to VGA Palette Snoop. This bit is hardwired to By writing a 1 to this bit SERR# Status. Read as BMIBA-Bus Master Interface Base Address Register Function MLT-Master Latency Timer Register FunctionBus Master interface registers and correspond to AD154 SID-Subsystem ID Function SVID-Subsystem Vendor ID FunctionIDETIM-IDE Timing Register Function SIDETIM-Slave IDE Timing Register Function Bit Description Reserved DMACTL-Synchronous DMA Control Register Function SDMATIM-Synchronous DMA Timing Register Function Ultra DMA/33 Timing Mode Settings BMICx-Bus Master IDE Command Register I/OIDE Controller I/O Space Registers Ultra DMA/33 Timing Modes BMISx-Bus Master IDE Status Register I/O Is equal to the IDE device transfer size Interrupt/Activity Status Combinations312 12-12 PCI Configuration Registers-Function Universal Serial Bus USB ConfigurationUsbren Bit Description 1510 Reserved. Read USB Host Controller Register Descriptions PCI FunctionReserved. Read as Reserved. Read as 0’s Resets STA to 0 by writing a 1 to this bit Register in Function This field13-4 INTLN-Interrupt Line Register Function USBBA-USB I/O Space Base Address Function Miscellaneous Control Function INTPN-Interrupt Pin FunctionSBRNUM-Serial Bus Release Number Function LEGSUP-Legacy Support Register Function Needs to be serviced later Default to 1 for compatibility with older USB softwareAppropriate enable bits are set Accesses that are part of the sequence USBCMD-USB Command Register I/O USBREN-USB Resume EnableUSB Host Controller I/O Space Registers Swdbg Bit Run/Stop Bit Operation Run/Stop, Debug Bit InteractionStop=0, the Frnum register can be reprogrammed By Software or Hardware USBSTS-USB Status Register I/O USBINTR-USB Interrupt Enable Register I/OInterrupt is generated to the system Register = FRNUM-Frame Number Register I/O Address signalsFLBASEADD-Frame List Base Address Register I/O SOFMOD-Start of Frame SOF Modify Register I/O PORTSC-Port Status and Control Register I/O Asserted, the corresponding port is disabled X0 DisableEOF2 time See of the USB Specification Register define the hub states as follows 13-14 SM Bus Configuration Registers Function SM Bus Controller ConfigurationClass Code 0C-1Fh Reserved Base Address Register Shutdown special cycle System Management Register Descriptions14-2 STA to 0 by writing a 1 to this bit 14-4 SMBBA-SMBus Base Address Function Interrupt pin PIRQB# is used Host Configuration SMBus I/O Space Registers Smbslvc-SMBus Slave Command FunctionSmbshdw1-SMBus Slave Shadow Port 1 Function Smbshdw2-SMBus Slave Shadow Port 2 Function Smbhststs-SMBus Host Status Register I/O Transaction errors are caused bySmbslvsts-SMBus Slave Status Register I/O Position Smbhstcnt-SMBus Host Control Register I/O Command field of SMBus host transaction Smbhstcmd-SMBus Host Command Register I/OSmbhstadd-SMBus Host Address Register I/O Smbhstdat0-SMBus Host Data 0 Register I/O Smbblkdat-SMBus Block Data Register I/O Smbhstdat1-SMBus Host Data 1 Register I/OSmbslvcnt-SMBus Slave Control Register I/O Smbslvdat-SMBus Slave Data Register I/O 14.3.9.1 Smbshdwcmd -SMBus Shadow Command Register I/O14.3.9.2 10.3.11.smbslvevt-SMBus Slave Event Register I/O Address 10h or one of the slave shadow port addresses 14-12 PCI Interface PCI/LPC Bridge DescriptionInterrupt Controller Programming the Interrupt Controller Initialization Command Words ICWs15-2 Automatic End of Interrupt Aeoi Mode Operation Command Words OCWsEnd of Interrupt Operation End of Interrupt EOI Special Fully Nested Mode Fully Nested ModeModes of Operation Automatic Rotation Equal Priority Devices Poll Command Cascade ModeSpecific Rotation Specific Priority Special Mask Mode Edge and Level Triggered ModeInterrupt Masks Masking on an Individual Interrupt Request Basis Interrupt Steering Reading the Interrupt Controller Status Continuous Idle Mode Quiet Active ModeSerial Interrupts Protocol Serirq Frames Stop FrameData Frame Number Usage # Clocks Past Start 3222 Programming the Interval Timer Timer/Counters15-10 Write Operations Interval Timer Control Word Format Read Operations Counter Latch CommandCounter I/O Port Read 15-12 Real Time Clock Read Back Command RTC Standard RAM Bank RTC Registers and RAMIndex Address Name 1 Invalid 0 Invalid 15.5.1.1 Register a90625 ms 8125 ms 15.5.1.3 Register C 15.5.1.2 Register BRSMRST# RTC Interrupts RTC Update CycleLockable RAM Ranges 15.5.1.4 Register D 15-18 IFB Power States and Consumption IFB Power ManagementOverview Acpi State Description Power Plane Descriptions IFB Power Planes16.2.2 SMI# Generation Causes of SMI# Sleep States SCI GenerationCauses of SCI# SCI Event Comment Entry/Exit for the S4 and S5 States Acpi Bits Not Implemented by IFBAcpi Bits Not Implemented in IFB Offset Register Name/Function Comment Action after Power Returns Handling of Power Failures in IFBS5 Wake Event Comment 16-6