WXB Hot-Plug

11:8 reserved(0)

7Enable PCI Configuration Space Access to Hot-Plug Registers. Enables IHPC memory- mapped register access through the index register (configuration offset 50h) and data port (configuration offset 54h).

6:2 reserved (0)

1reserved (1)

0On / Off Busy (OOBS) status. Read Only. Same as bit 24 of the memory-mapped Hot- Plug Miscellaneous register.

8.1.18Hot-Plug Features

Address Offset:

44h-45

Size:

16 bits

Default Value:

0000h

Attribute:

Read Only

Definitions of each bit within this register are expected to be constant through the industry but are, as of yet, undefined.

Bits Description

15:0 reserved (0)

8.1.19Switch Change SERR Status

Address Offset:

48h

Size:

8 bits

Default Value:

00h

Attribute:

Partial Read/Write

Bits

Description

 

 

 

7:6

reserved (0)

 

 

 

5:0 Switch Change SERR Status. Slot F is MSB. Slot A is LSB. Similar to the Power Fault SERR status register, but applicable to switch changes when the switch interrupt redirect bit for a slot is set and the associated interrupt mask bit is logic 0. Unlike the Power Fault SERR status register, clearing this bit will also clear the associated interrupt.

8.1.20Power Fault SERR Status

Address Offset:

49h

Size:

8 bits

Default Value:

00h

Attribute:

Partial Read/Write

Bits

Description

 

 

 

7:6

reserved.

 

 

 

5:0

Power Fault SERR Status. If the power fault function enable bit and the SERR on power

 

fault bit are both set, then these six bits will indicate (by a logic 1, one for each slot) if a

 

power fault has occurred while a slot was connected to the bus or clock. Slot F is MSB.

Slot A is LSB. These bits can be cleared by writing a logic 1 to the appropriate position. This register does not effect PCI interrupts.

Intel® 460GX Chipset Software Developer’s Manual

8-9